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M34D64 Datasheet(PDF) 3 Page - STMicroelectronics

Part No. M34D64
Description  64 Kbit Serial I2C Bus EEPROM With Hardware Write Control on Top Quarter of Memory
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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M34D64 Datasheet(HTML) 3 Page - STMicroelectronics

 
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M34D64
SIGNAL DESCRIPTION
Serial Clock (SCL)
This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor must be con-
nected from Serial Clock (SCL) to VCC. (Figure 5
indicates how the value of the pull-up resistor can
be calculated). In most applications, though, this
method of synchronization is not employed, and
so the pull-up resistor is not necessary, provided
that the bus master has a push-pull (rather than
open drain) output.
Serial Data (SDA)
This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to VCC. (Fig-
ure 5 indicates how the value of the pull-up resistor
can be calculated).
Chip Enable (E0, E1, E2)
These input signals are used to set the value that
is to be looked for on the three least significant bits
(b3, b2, b1) of the 7-bit Device Select Code. These
inputs must be tied to VCC or VSS, to establish the
Device Select Code.
Write Control (WC)
The hardware Write Control pin (WC) is useful for
protecting the top quarter of the memory (as
shown in Figure 4) from inadvertent erase or write.
The Write Control signal is used to enable
(WC=VIL) or disable (WC=VIH) write instructions to
the top quarter of the memory area. When uncon-
nected, the WC input is internally read as VIL, and
write operations are allowed.
Figure 4. Memory Map showing Write Control
Area
Figure 5. Maximum RL Value versus Bus Capacitance (CBUS) for an I
2C Bus
AI03114C
1FFFh
Write Controlled
Area
1000h
0000h
0800h
1800h
AI01665
VCC
CBUS
SDA
RL
MASTER
RL
SCL
CBUS
100
0
4
8
12
16
20
CBUS (pF)
10
1000
fc = 400kHz
fc = 100kHz


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