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XRD54L12AID Datasheet(PDF) 6 Page - Exar Corporation |
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XRD54L12AID Datasheet(HTML) 6 Page - Exar Corporation |
6 / 16 page XRD54L08/L10/L12 6 Rev. 1.30 TIMING CS SCLK SDIN DOUT tCSW tCS1 tCSH1 tCL tD0 tDH tDS tCH tCSS tCSH0 Figure 2. Timing Diagram Input Output 1111 1111 (0000) 1000 0001 (0000) 1000 0000 (0000) 0111 1111 (0000) 0000 0001 (0000) 0000 0000 (0000) 0V Note: Write 8-bit data words with four sub-LSB 0s because the DAC input latch is 12 bits wide. Table 1. Binary Code Table + 2 (VREFIN) 127 256 + 2 (VREFIN) 129 256 + 2 (VREFIN) 255 256 + 2 (VREFIN) 128 256 = + VREFIN + 2 (VREFIN) 1 256 |
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