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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

WEDPY256K72V-XBX

August 2004

Rev. 7

NOTES:

1. DQ (A2) refers to output from address A2. DQ (A2+ 1) refers to output from the next internal burst address following A2.

2. CS2# and CS2# have timing identical to CS1#. On this diagram. When CS1 is LOW, CS2# is LOW and CS2# is HIGH.

When CS1# is HIGH, CS2# is HIGH and CS2 is LOW.

3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q to

be driven until after the following clock rising edge.

4. Outputs are disabled within two clock cycles after deselect.

CLK

A1

A2

(NOTE 3)

ADV# suspends burst

Deselect cycle (Note 4)

(NOTE 1)

High-Z

Single READ

Burst Read Cycle

Burst wraps around

to its initial state

Burst continued with new base address

A3

Don’t care

Undefined

ADSP#

ADSC#

Address

GW#, BWE#

BWa-BWd

(Note 2)

ADV#

OE#

Q#

Q(A1)

Q(A2)

Q(A2+2)

Q(A2+3)

Q(A2+1)

Q(A2)

Q(A3)

Q

(A2+1)