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WED2DG472512V-D2 Datasheet(PDF) 1 Page - White Electronic Designs Corporation |
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WED2DG472512V-D2 Datasheet(HTML) 1 Page - White Electronic Designs Corporation |
1 / 10 page 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED2DG472512V-D2 January 2000 Rev. 0 ADVANCED* White Electronic Designs Corp. reserves the right to change products or specifications without notice. DESCRIPTION 16MB (4x512Kx72) SYNC BURST-PIPELINE, DUAL KEY DIMM The WED2DG472512V is a Synchronous/Synchronous Burst SRAM, 84 position Dual Key; Double High DIMM (168 contacts) Module, organized as 4x512Kx72. The Module contains sixteeen (16) Synchronous Burst RAM devices, packaged in the industry standard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4 Substrate. The Module Architecture is defined as a Sync/SyncBurst, Pipeline, with support for either linear or sequential burst. This Module provides high performance, 3-1-1-1 accesses when used in Burst Mode, and when used in Synchronous Only Mode, provides a high performance, data access every second cycle. Synchronous Only operations are performed via strapping ADSC# Low, and ADSP#/ADV# High, which provides for Ultra Fast Accesses in Read Mode while providing for internally self-timed Early Writes. Synchronous/Synchronous Burst operations are in relation to an externally supplied clock, Registered Address, Registered Global Write, Registered Enables as well as an Asynchronous Output Enable. This Module has been defined with full flexibility, which allows individual control of each of the eight bytes, as well as Quad Words in both Read and Write Operations. * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. FEATURES 4x512Kx72 Synchronous, Synchronous Burst Pipeline Architecture; Single Cycle Deselect Linear and Sequential Burst Support via MODE pin Clock Controlled Registered Module Enable (EM#) Clock Controlled Registered Bank Enables (E1#, E2#, E3#, E4#) Clock Controlled Byte Write Mode Enable (BWE#) Clock Controlled Byte Write Enables (BW1# - BW8#) Clock Controlled Registered Address Clock Controlled Registered Global Write (GW#) Asynchronous Output Enable (G#) Internally Self-Timed Write Individual Bank Sleep Mode Enables (ZZ1, ZZ2, ZZ3, ZZ4) Gold Lead Finish 3.3V ± 10% Operation Frequency(s): 200, 166, 150, and 133MHz Access Speed(s): tKHQV = 3.0, 3.5, 3.7, and 4.0ns Common Data I/O High Capacitance (30pF) Drive, at Rated Access Speed Single Total Array Clock Multiple Vcc and Gnd for Improved Noise Immunity |
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