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W3HG2128M72ACERXXXAD6SG Datasheet(PDF) 6 Page - White Electronic Designs Corporation |
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W3HG2128M72ACERXXXAD6SG Datasheet(HTML) 6 Page - White Electronic Designs Corporation |
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6 / 13 page  W3HG2128M72ACER-AD6 PRELIMINARY 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs May 2006 Rev. 5 AC TIMING PARAMETERS 0°C ≤ TCASE < +85°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V AC CHARACTERISTICS 806 667 534 403 PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNIT Notes Clock cycle time CL = 6 tCK (6) TBD TBD ps 16, 24 CL = 5 tCK (5) TBD TBD 3,000 8,000 ps 16, 24 CL = 4 tCK (4) TBD TBD 3,750 8,000 3,750 8,000 5,000 8,000 ps 16, 24 CL = 3 tCK (3) TBD TBD 5,000 8,000 5,000 8,000 5,000 8,000 ps 16, 24 CK high-level width tCH TBD TBD 0.45 0.55 0.45 0.55 0.45 0.55 tCK 18 CK low-level width tCL TBD TBD 0.45 0.55 0.45 0.55 0.45 0.55 tCK 18 Half clock period tHP TBD TBD MIN (tCH, tCL) MIN (tCH, tCL) MIN (tCH, tCL) ps 19 DQ output access time from CK/CK# tAC TBD TBD -450 +450 -500 +500 -600 +600 ps Data-out high-impedance window from CK/CK# tHZ TBD TBD tAC (MAX) tAC MAX tAC MAX ps 8, 9 Data-out low-impedance window from CK/CK# tLZ TBD TBD tAC (MIN) tAC (MAX) tAC (MIN) tAC (MAX) tAC (MIN) tAC (MAX) ps 8, 10 DQ and DM input setup time relative to DQS tDSa TBD TBD 300 350 400 ps 7, 15, 21 DQ and DM input hold time relative to DQS tDHa TBD TBD 300 350 400 ps 7, 15, 21 DQ and DM input setup time relative to DQS tDSb TBD TBD 100 100 150 tCK 7, 15, 21 DQ and DM input hold time relative to DQS tQHb TBD TBD 175 225 275 ps 7, 15, 21 DQ…DQS hold, DQS to first DQ to go nonvalid, per access relative to DQS tDIPW TBD TBD 0.35 0.35 0.35 ps Data hold skew factor tQHS TBD TBD 340 400 450 DQ–DQS hold, DQS to first DQ to go nonvalid, per access tQH TBD TBD tHP- tQHS tHP- tQHS tHP- tQHS 15, 17 Data valid output window (DVW) tDVW TBD TBD tQH- tDQSQ tQH- tDQSQ tQH- tDQSQ 15, 17 DQS input high pulse width tDQSH TBD TBD 0.35 0.35 0.35 tCK DQS input low pulse width tDQSL TBD TBD 0.35 0.35 0.35 tCK DQS output access time from CK/CK# tDQSCK TBD TBD -400 +400 -450 +450 -500 +500 ps DQS falling edge to CK rising– setup time tDSS TBD TBD 0.2 0.2 0.2 tCK DQS falling edge from CK rising – hold time tDSH TBD TBD 0.2 0.2 0.2 tCK DQS–DQ skew, DQS to last DQ valid, per group, per access tDQSQ TBD TBD 240 300 350 ps 15, 17 DQS read preamble tRPRE TBD TBD 0.9 1.1 0.9 1.1 0.9 1.1 tCK 35 NOTE: • AC specification is based on MICRON components. Other DRAM manufactures specification may be different. |
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