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W3HG128M64EEUXXXD4SG Datasheet(PDF) 6 Page - White Electronic Designs Corporation |
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W3HG128M64EEUXXXD4SG Datasheet(HTML) 6 Page - White Electronic Designs Corporation |
6 / 14 page W3HG128M64EEU-D4 March 2006 Rev. 0 ADVANCED 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs AC OPERATING CONDITIONS VCC = +1.8V ±0.1V AC Characteristics Symbol 806 665 534 403 Units Notes Parameter Min Max Min Max Min Max Min Max Clock cycle time CL = 6 tCK (6) 3,000 8,000 ------ ps CL = 5 tCK (5) 3,000 8,000 3,000 8,000 ---- ps 16, 22, 36, 38 CL = 4 tCK (4) 3,000 8,000 3,750 8,000 3,750 8,000 5,000 8,000 ps CL = 3 tCK (3) - - 5,000 8,000 5,000 8,000 5,000 8,000 ps CK high-level width tCHAVG 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 t CK 45 CK low-level width tCLAVG 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 t CK Half clock period tHP MIN ( tCH,tCL) MIN ( tCH,tCL) MIN ( tCH,tCL) MIN ( tCH,tCL) ps 46 Absolute tCk tCKabs t CKAVG+ (MIN)+ t JITPER (MIN) t CKAVG+ (MAX)+ t JITPER (MAX) t CKAVG+ (MIN)+ t JITPER (MIN) t CKAVG+ (MAX)+ t JITPER (MAX) t CKAVG+ (MIN)+ t JITPER (MIN) t CKAVG+ (MAX)+ t JITPER (MAX) t CKAVG+ (MIN)+ t JITPER (MIN) t CKAVG+ (MAX)+ t JITPER (MAX) ps Absolute CK high-level width tCHabs t CKAVG (MIN)* t CH AVG+ t JIT DTY(MIN) t CKAVG (MAX)* t CH AVG+ t JIT DTY(MAX) t CKAVG (MIN)* t CH AVG+ t JIT DTY(MIN) t CKAVG (MAX)* t CH AVG+ t JIT DTY(MAX) t CKAVG (MIN)* t CH AVG+ t JIT DTY(MIN) t CKAVG (MAX)* t CH AVG+ t JIT DTY(MAX) t CKAVG (MIN)* t CH AVG+ t JIT DTY(MIN) t CKAVG (MAX)* t CH AVG+ t JIT DTY(MAX) ps Absolute CK low-level width tCLabs t CKAVG (MIN)* t CLAVG (MIN)+ t JIT DTY(MIN) t CKAVG (MAX)* t CLAVG (MAX)+ t JIT DTY(MIN) t CKAVG (MIN)* t CLAVG (MIN)+ t JIT DTY(MIN) t CKAVG (MAX)* t CLAVG (MAX)+ t JIT DTY(MIN) t CKAVG (MIN)* t CLAVG (MIN)+ t JIT DTY(MIN) t CKAVG (MAX)* t CLAVG (MAX)+ t JIT DTY(MIN) t CKAVG (MIN)* t CLAVG (MIN)+ t JIT DTY(MIN) t CKAVG (MAX)* t CLAVG (MAX)+ t JIT DTY(MIN) ps Clock jitter - period tJITPER -125 125 -125 125 -125 125 -125 125 ps 39 Clock jitter - half period tJITDUTY -125 125 -125 125 -125 125 -150 150 ps 40 Clock jitter - cycle to cycle tJITCC 250 250 250 250 ps 41 Cumulative jitter error, 2 cycles tERR2per -175 175 -175 175 -175 175 -175 175 ps 42 Cumulative jitter error, 3 cycles tERR3per -225 225 -225 225 -225 225 -225 225 ps 42 Cumulative jitter error, 4 cycles tERR4per -250 250 -250 250 -250 250 -250 250 ps 42 Cumulative jitter error, 5cycles tERR5per -250 250 -250 250 -250 250 -250 250 ps 42, 48 Cumulative jitter error, 6-10 cycles tERR6-10per -350 350 -350 350 -350 350 -350 350 ps 42, 48 Cumulative jitter error, 11-50 cycles tERR11-50per -450 450 -450 450 -450 450 -450 450 ps 42 Note: • AC specification is based on MICRON components. Other DRAM manufactures specification may be different. |
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