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EM6622 Datasheet(PDF) 23 Page - EM Microelectronic - MARIN SA |
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EM6622 Datasheet(HTML) 23 Page - EM Microelectronic - MARIN SA |
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23 / 70 page  EM6622 03/02 REV. C/445 Copyright 2002, EM Microelectronic-Marin SA 23 www.emmicroelectronic.com 6.6.5 Detailed Functional Description Master or Slave mode is selected in the control register RegSCntl1. In Slave mode, the serial clock comes from an external device and is input via the PSP[3] terminal as a synchronous clock (SCLKIn) to the serial interface. The serial clock is ignored as long as the Start bit is not set. After setting Start, only the eight following active edges of the serial clock input PSP[3] are used to shift the serial data in and out. After eight serial clock edges the Start bit is reset. The PSP[1] terminal is a copy of the (Start OR Status) bit values, it can be used to indicate to the external master, that the interface is ready to operate or it can be used as a chip select signal in case of an external slave. In Master mode, the synchronous serial clock is generated internally from the system clock. The frequency is selected from one out of three sources ( MS0 and MS1 bits in RegSCntl1) . The serial shifting clock is only generated during Start = high and is output to the SCLK terminal as the Master Clock (SCLKOut). When Start is low, the serial clock output on PSP[3] is 0. An interrupt request IRQSerial is generated after the eight shift operations are done. This signal is set by the last negative edge of the serial interface clock on PSP[3] (master or slave mode) and is reset to 0 by the next write of Start or by any reset. This interrupt can be masked with register RegIRQMask3. For more details about the interrupt handling see chapter 10. Serial data input on PSP[0] is sampled by the positive or negative serial shifting clock edge, as selected by the Control Register POSnNeg bit. Serial data input is shifted in LSB first or MSB first, as selected by the Control Register MSBnLSB bit. 6.6.6 Output Modes Serial data output is given out in two different ways (Refer also to Figure 16 and Figure 17). - OM[1] = 1, OM[0] = 0 : The serial output data is generated with the selected shift register clock (POSnNeg). The first data bit is available directly after the Start bit is set. -OM[1] = 0, OM[0] = 1 : The serial output data is re-synchronized by the positive serial interface clock edge, independent of the selected clock shifting edge. The first data bit is available on the first positive serial interface clock edge after Start=‘1’. Table 6.6.6 Output Mode Selection in RegSCntl2 OM[1] OM[0] Output mode Description 0 0 Tristate Output disable (tristate on PSP[3:0]) 01 Serial- Synchronized Re-synchronized positive edge data shift out 1 0 Serial-Direct Direct shift pos. or neg. edge data out 1 1 Parallel Parallel port SP output Tristate output is selected by default. Figure 16. Direct or Re-Synchronized Output bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 SIN SOUT +ve/-ve Edge Direct Shift Out bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 M U X bit4 bit5 bit6 bit7 bit0 bit[n ] bit1 bit2 bit3 +ve Edge clock SIN SOUT +ve/-ve Edge Re-synchronised shift out M U X bit3 bit2 bit1 bit0 bit7 bit6 bit5 bit4 MSBnLSB |
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