 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
EM6621 Datasheet(PDF) 20 Page - EM Microelectronic - MARIN SA |
|
||||||||||||||||||||||||||||||
EM6621 Datasheet(HTML) 20 Page - EM Microelectronic - MARIN SA |
|
|
20 / 69 page  EM6621 © EM Microelectronic-Marin SA, 03/99, Rev. B/ 03/02 REV. D/444 Copyright 2002, EM Microelectronic-Marin SA 20 www.emmicroelectronic.com 6.6 Port Serial The EM6621 contains a simple, half duplex three wire synchronous type serial interface., which can be used to program or read an external EEPROM, ADC, ... etc. For data reception, a shift-register converts the serial input data on the SIN(PSP[0]) terminal to a parallel format, which is subsequently read by the CPU in registers RegSDataL and RegSDataH for low and high nibble. To transmit data, the CPU loads data into the shift register, which then serializes it on the SOUT(PSP[2]) terminal. It is possible for the shift register to simultaneously shift data out on the SOUT terminal and shift data on the SIN terminal. In Master mode, the shifting clock is supplied internally by the Prescaler : one of three prescaler frequencies are available, Ck[16], Ck[15] or Ck[14]. In Slave mode, the shifting clock is supplied externally on the SCLKIn(PSP[3]) terminal. In either mode, it is possible to program : the shifting edge, shift MSB first or LSB first and direct shift output. All these selection are done in register RegSCntl1 and RegSCntl2. The PSP[3..0] terminal configuration is shown in Figure 14. When the Serial Interface is active then : ∗ PSP[1] {Ready / CS) is outputting the ready (slave mode) or the CS signal (master mode). ∗ PSP[2] {SOUT} is always an output. ∗ PSP[0] {SIN} is always an input. ∗ PSP[3] {SCLK} is an output for Master mode {SCLKOut} and an input for Slave mode {SCLKIn} 6.6.1 4-bit Parallel I/O Selecting OM[1],OM[0] = ‘1’ in register RegSCntl2 the PSP[3:0] terminals are configured as a 4-bit Output. Output data is stored in the register RegSPData . The RegSPData is defined as a read/write register, but what is read is not the register output, but the port PSP[3:0] terminal values Selecting OM[1],OM[0] = ‘0’ in register RegSCntl2 the PSP[3:0] outputs are cut off (tristate). The terminals can be used as inputs with individual (bit-wise) pull-up or pull-down settings. Independent of the selected configuration, the PSP[3:0] terminal levels are always readable. Figure 13. Serial Interface Architecture Shift Complete (8th Shift Clock) 8 Bit Shift Register Serial Input Data from SIN IRQSerial Serial Output Data to SOUT Terminal Serial Master Clock Output SCLKOut to SCLK Terminal Internal Master Clock Source (from Prescaler) M U X External Slave Clock Source (SCLKIn from SCLK terminal) Mode Start Direct MSB/LSB Status Shift First Control Logic Clock Enable Shift CK Status to CS/ Ready Terminal Control & Status Registers Reset Start W rite Read Tx Rx 4-Bit Internal Data Bus High-Z to all SP[3:0] Terminals |
Similar Part No. - EM6621 |
|
Similar Description - EM6621 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
