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EM6620 Datasheet(PDF) 2 Page - EM Microelectronic - MARIN SA

Part No. EM6620
Description  Ultra Low Power Microcontroller with 4x8 LCD Driver
Download  56 Pages
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Maker  EMMICRO [EM Microelectronic - MARIN SA]
Homepage  http://www.emmicroelectronic.com
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EM6620 Datasheet(HTML) 2 Page - EM Microelectronic - MARIN SA

 
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R
EM6620
Copyright
© 2005, EM Microelectronic-Marin SA
2
www.emmicroelectronic.com
EM6620 at a glance
Power Supply
- Low voltage low power architecture
including internal voltage regulator
- 1.2 ... 3.6 V battery voltage
- 2.1 µA in active
mode (Xtal, LCD on, 25
°C)
- 0.5 µA in standby mode (Xtal, LCD off, 25
°C)
- 0.1 µA in sleep
mode (25
°C)
- 32 KHz Oscillator
• RAM
- 64 x 4 bit, direct addressable
• ROM
- 1280 x 16 bits, metal mask programmable
• CPU
- 4 bit RISC architecture
- 2 clock cycles per instruction
- 72 basic instructions
Main Operating Modes and Resets
- Active Mode
(CPU is running)
- Standby Mode (CPU in halt)
- Sleep Mode
(no clock, reset state)
- Initial reset on power on (POR)
- Watchdog reset (logic and oscillation watchdogs)
- Reset with input combination on port A (register
selectable)
Liquid Crystal Display Driver (LCD)
- 8 segments 3 or 4 times multiplexed
- Internal or external voltage multiplier
- Free segment allocation architecture
(metal 2 mask)
- LCD switch off for power save
4-Bit Input Port A
- Direct input read on the port terminals
- Debouncer function available on all inputs
- Interrupt request on positive or negative edge
- Pull-up or pull-down or none selectable by
register
- Test variables (software) for conditional jumps
- PA[0] and PA[3] are inputs for the event counter
- PA[3] is Start/Stop input for the millisecond
counter
- Reset with input combination (register selectable)
Prescaler
- 15 stage system clock divider down to 1Hz
- 3 Interrupt requests; 1Hz, 32Hz or 8Hz, Blink
- Prescaler reset (4kHz to 1Hz)
4-Bit Bi-directional Port B
-
All different functions bit-wise selectable
- Direct input read on the port terminals
- Data output latches
- CMOS or Nch. open drain outputs
- Pull-down or pull-up selectable
- Weak pull-up in Nch. open drain mode
- Selectable PWM, 32kHz, 1kHz and 1Hz output
- Dynamic Input Comparator on PB[0] (SVLD level)
Voltage Level Detector
- Mask selectable level, default 2.0V
- Busy flag during measure
- Interrupt request at end of measure
10-Bit Universal Counter
- 10, 8, 6 or 4 bit up/down counting
- Parallel load
- Event counting (PA[0] or PA[3])
- 8 different input clocks-
- Full 10 bit or limited (8, 6, 4 bit) compare function
- 2 interrupt requests (on compare and on 0)
- Hi-frequency input on PA[3] and PA[0]
- Pulse width modulation (PWM) output
Millisecond Counter
- 3 digits binary coded decimal counter (12 bits)
- PA[3] signal pulse width and period measurement
- Internal 1000 Hz clock generation
- Hardware or software controlled start stop mode
- Interrupt request on either 1/10 Sec or 1Sec
Interrupt Controller
- 5 external and 7 internal interrupt request sources
- Each interrupt request individually maskable
- Each interrupt flag individually resettable
- Automatic reset of each interrupt request register
after read
- General interrupt request to CPU can be disabled
- Automatic enabling of general interrupt request
flag when going into HALT mode


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