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EM6617 Datasheet(PDF) 27 Page - EM Microelectronic - MARIN SA

Part No. EM6617
Description  Ultra Low Power Microcontroller with ADC AND EEPROM
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Maker  EMMICRO [EM Microelectronic - MARIN SA]
Homepage  http://www.emmicroelectronic.com
Logo EMMICRO - EM Microelectronic - MARIN SA

EM6617 Datasheet(HTML) 27 Page - EM Microelectronic - MARIN SA

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EM6617
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8.6 Counter Setup
RegCDataL[3:0], RegCDataM[3:0], RegCDataH[1:0] are used to store the initial count value called CReg[9:0]
which is written into the count register bits
Count[9:0] when writing the bit Load to ‘1’ in RegCCntl2. This bit is
automatically reset thereafter. The counter value
Count[9:0] can be read out at any time, except when using
non-debounced high frequency port A input clock. To maintain data integrity the lower nibble
Count[3:0] must
always be read first. The
ShCount[9:4] values are shadow registers to the counter. To keep the data integrity
during a counter read operation (3 reads), the counter values [9:4] are copied into these registers with the read of
the count[3:0] register. If using non-debounced high frequency port A input the counter must be stopped while
reading the
Count[3:0] value to maintain the data integrity.
In down count mode an interrupt request
IRQCount0 is generated when the counter reaches 0. In up count
mode, an interrupt request is generated when the counter reaches 3FF (or FF,3F,F if limited bit counting).
Never an interrupt request is generated by loading a value into the counter register.
When the counter is programmed from up into down mode or vice versa, the counter value
Count[9:0] gets
inverted. As a consequence, the initial value of the counter must be programmed after the
Up/Down selection.
Loading the counter with hex 000 is equivalent to writing stop mode, the
Start bit is reset, no interrupt request is
generated.
How to use the counter;
If PWM output is required one has to put the port B[3] in output mode and set PWMOn=1 in step 5.
1st,
set the counter into stop mode (
Start=0).
2nd,
select the frequency and up- or down count mode in
RegCCntl1.
3rd,
write the data registers
RegCDataL, RegCDataM, RegCDataH (counter start value and length)
4th,
load the counter,
Load=1, and choose the mode. (EvCount, EnComp=0)
5th,
select bits
PWMOn in RegPresc and SelIntFull in RegSysCntl1
6th,
if compare mode desired , then write
RegCDataL, RegCDataM, RegCDataH (compare value)
7th,
set bit
Start and select EnComp in RegCCntl2
8.7 10-bit Counter Registers
Table 8.7.1 Register RegCCntl1
Bit
Name
Reset
R/W
Description
3
Up/Down
0
R/W
Up or down counting
2
CountFSel2
0
R/W
Input clock selection
1
CountFSel1
0
R/W
Input clock selection
0
CountFsel0
0
R/W
Input clock selection
Default : PA0 ,selected as input clock, Down counting
Table 8.7.2 Counter Input Frequency Selection with CountFSel[2..0]
CountFSel2
CountFSel1
CountFSel0
clock source selection
0
0
0
Port A
PA[0]
0
0
1
Prescaler Ck[15]
0
1
0
Prescaler Ck[12]
0
1
1
Prescaler Ck[10]
1
0
0
Prescaler Ck[8]
1
0
1
Prescaler Ck[4]
1
1
0
Prescaler Ck[1]
1
1
1
Port A
PA[3]


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