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EM6617 Datasheet(PDF) 24 Page - EM Microelectronic - MARIN SA

Part No. EM6617
Description  Ultra Low Power Microcontroller with ADC AND EEPROM
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Maker  EMMICRO [EM Microelectronic - MARIN SA]
Homepage  http://www.emmicroelectronic.com
Logo EMMICRO - EM Microelectronic - MARIN SA

EM6617 Datasheet(HTML) 24 Page - EM Microelectronic - MARIN SA

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EM6617
Copyright
© 2005, EM Microelectronic-Marin SA
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8.2 Frequency Select and Up/Down Counting
8 different input clocks can be selected to drive the Counter. The selection is done with bits
CountFSel2…0 in
register
RegCCntl1. 6 of this input clocks are coming from the prescaler. The maximum prescaler clock frequency
for the counter is half the system clock and the lowest is 1Hz. Therefore a complete counter roll over can take as
much as 17.07 minutes (1Hz clock, 10 bit length) or as little as 977
µs (Ck[15], 4 bit length). The IRQCount0,
generated at each roll over, can be used for time bases, measurements length definitions, input polling, wake up
from Halt mode, etc. The
IRQCount0 and IRQComp are generated with the system clock Ck[16] rising edge.
IRQCount0 condition in up count mode is : reaching 3FF if 10-bit counter length (or FF, 3F, F in 8, 6, 4-bit counter
length). In down count mode the condition is reaching ‘0’. The non-selected bits are ‘don’t care’. For IRQComp
refer to section 8.4.
Note:
The Prescaler
and the Microprocessor clock’s are usually non-synchronous, therefore time bases
generated are max. n, min. n-1 clock cycles long (n being the selected counter start value in count down mode).
However the prescaler clock can be synchronized with µP commands using for instance the prescaler reset
function.
The two remaining clock sources are coming from the PA[0] or PA[3] terminals. Refer to the Figure 12 on page
14 for details. Both sources can be either debounced (Ck[11] or Ck[8]) or direct inputs, the input polarity can also
be chosen. The output after the debouncer polarity selector is named PA3 , PA0 respectively. For the debouncer
and input polarity selection refer to chapter 7.2.4.
In the case of port A input clock without debouncer, the counting clock frequency will be half the input clock on
port A. The counter advances on every odd numbered port A negative edge ( divided clock is high level ).
IRQCount0 and IRQComp will be generated on the rising PA3 or PA0 input clock edge. In this condition the
EM6617 is able to count with a higher clock rate as the internal system clock (Hi-Frequency Input). Maximum port
A input frequency is limited to 200kHz. If higher frequencies are needed, please contact EM-Marin.
In both, up or down count (default) mode, the counter is cyclic. The counting direction is chosen in register
RegCCntl1 bit Up/Down (default ‘0’ is down count). The counter increases or decreases its value with each
positive clock edge of the selected input clock source. Start up synchronization is necessary because one can not
always know the clock status when enabling the counter. With EvCount=0, the counter will only start on the next
positive clock edge after a previously latched negative edge, while the
Start bit was already set to ‘1’. This
synchronization is done differently if event count mode (bit
EvCount) is chosen. Refer also to Figure 19. Internal
Clock Synchronization.
Figure 18. Counter Clock Timing
P r e s c a le r F r eq ue nc ie s o r D e bo un c e d P o r t A C lo c k s
N o n - D e b o u n ce d P o r t A C lo cks ( S yste m C lo ck In d e p e n d e n t)
S yste m C lo c k
P r e sca le r C lo c k
Co u n tin g
C o u n te r IR Q ’s
D iv ide d C lo c k
S yste m C lo c k
Po r t A C lo c k
Co u n tin g
C o u n te r IR Q ’s


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