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EM6617 Datasheet(PDF) 19 Page - EM Microelectronic - MARIN SA

Part No. EM6617
Description  Ultra Low Power Microcontroller with ADC AND EEPROM
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Maker  EMMICRO [EM Microelectronic - MARIN SA]
Homepage  http://www.emmicroelectronic.com
Logo EMMICRO - EM Microelectronic - MARIN SA

EM6617 Datasheet(HTML) 19 Page - EM Microelectronic - MARIN SA

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EM6617
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© 2005, EM Microelectronic-Marin SA
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7.4.4 PWM and Frequency Output
PB[3] can also be used to output the PWM (Pulse Width Modulation) signal from the 10-Bit Counter, the Ck[11],
Ck[16] as well as the Ck[12] prescaler frequencies.
-Selecting PWM
output on PB[3] with bit
PWMOn in register RegPresc and running the counter.
-Selecting Ck[11] output on PB[2] with bit
PB1kHzOut in register OPTFSelPB
-Selecting Ck[16] output on PB[1] with bit
PB32kHzOut in register OPTFSelPB
-Selecting Ck[12 ] output on PB[0] with bit
PB2kHzOut in register OPTFSelPB
7.5 Port B registers
Table 7.5.1 Register RegPBData
Bit
Name
Reset
R/W
Description
3
PBData[3]
-
R/W*
PB[3] input and output
2
PBData[2]
-
R/W*
PB[2] input and output
1
PBData[1]
-
R/W*
PB[1] input and output
0
PBData[0]
-
R/W*
PB[0] input and output
R* : Direct read on pin (not the internal register read).
Table 7.5.2 Register RegPBCntl
Bit
Name
Reset
R/W
Description
3
PBIOCntl[3]
0
R/W
I/O control for PB[3]
2
PBIOCntl[2]
0
R/W
I/O control for PB[2]
1
PBIOCntl[1]
0
R/W
I/O control for PB[1]
0
PBIOCntl[0]
0
R/W
I/O control for PB[0]
Default "0" is: Port B in input mode
Table 7.5.3 Register OPTFSelPB
Bit
Name
power on
value
R/W
Description
3
PB1kHzOut
0
R/W
ck[11] output on PB[2]
2
PB32kHzOut
0
R/W
ck[16] output on PB[1]
1
PB2kHzOut
0
R/W
ck[12] output on PB[0]
0
InpResSleep
0
R/W
Reset From SLEEP with Port A
Default "0" is: No frequency output, port A Input reset can not reset the SLEEP mode.
Table 7.5.4 Option Register OPTNoPdPB
Bit
Name
power on
value
R/W
Description
3
NoPdPB[3]
0
R/W
No pull-down on PB[3]
2
NoPdPB[2]
0
R/W
No pull-down on PB[2]
1
NoPdPB[1]
0
R/W
No pull-down on PB[1]
0
NoPdPB[0]
0
R/W
No pull-down on PB[0]
Default "0" is: Pull-down on
Table 7.5.5 Option Register OPTNchOpDPB
Bit
Name
power on
value
R/W
Description
3
NchOpDPB[3]
0
R/W
N-Channel Open Drain on PB[3]
2
NchOpDPB[2]
0
R/W
N-Channel Open Drain on PB[2]
1
NchOpDPB[1]
0
R/W
N-Channel Open Drain on PB[1]
0
NchOpDPB[0]
0
R/W
N-Channel Open Drain on PB[0]
Default "0" is: CMOS on PB[3..0]


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