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EM6617 Datasheet(PDF) 14 Page - EM Microelectronic - MARIN SA

Part No. EM6617
Description  Ultra Low Power Microcontroller with ADC AND EEPROM
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Maker  EMMICRO [EM Microelectronic - MARIN SA]
Homepage  http://www.emmicroelectronic.com
Logo EMMICRO - EM Microelectronic - MARIN SA

EM6617 Datasheet(HTML) 14 Page - EM Microelectronic - MARIN SA

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EM6617
Copyright
© 2005, EM Microelectronic-Marin SA
14
www.emmicroelectronic.com
7.2 Port A
The EM6617 has one four bit general purpose CMOS input port. The port A input can be read at any time, internal
pull-up or pull-down resistors can be chosen. All selections concerning port A are bit-wise executable. I.e. Pull-up
on PA[2], pull-down on PA[0], positive IRQ edge on PA[0] but negative on PA[1], etc.
In sleep mode the port A pull-up or pull-down resistors are turned off, and the inputs are deactivated except if the
InpResSleep bit in the option register OPTFSelPB is set to 1. In this case the port A inputs are continuously
monitored to match the input reset condition which will immediately wake the EM6617 from sleep mode (all pull
resistors remain).
Figure 12. Input Port A Configuration
IntEdgPA[n]=0
NoDebIntPA[n]=1
Mask opt
MPAPU[n]
IRQPA[3:0]
PA[n]terminal
PA0, PA3
for 10-Bit
Counter
Mask opt
MPAPD[n]
Debouncer
µP TestVar
Ck[8]
Ck[11] or
Ck[14]
DB[3:0]
NoPullPA[n]
Vbat
(VDD)
VSS
Input Reset allowed
when in Sleep
Sleep
7.2.1 IRQ on Port A
For interrupt request generation (IRQ) one can choose direct or debouncer input and positive or negative edge
IRQ triggering. With the debouncer selected (
OPTDebIntPA ) the input must be stable for two rising edges of the
selected debouncer clock (
RegPresc). This means a worst case of 16 ms (default) or 2 ms (0.25 ms by metal
mask) with a system clock of 32 KHz.
Either a positive or a negative edge on the port A inputs - after debouncer or not - can generate an interrupt
request. This selection is done in the option register
OPTIntEdgPA.
All four bits of port A can provide an IRQ, each pin with its own interrupt mask bit in the
RegIRQMask1 register.
When an IRQ occurs, inspection of the
RegIRQ1, RegIRQ2 and RegIRQ3 registers allows the interrupt to be
identified and treated.
At power on or after any reset the
RegIRQMask1 is set to 0, thus disabling any input interrupt. A new interrupt is
only stored with the next active edge after the corresponding interrupt mask is cleared. See also the interrupt
chapter 13.
It is recommended to mask the port A IRQ’s while one changes the selected IRQ edge. Else one may generate a
IRQ (Software IRQ). I.e. PA[0] on ‘0’
then changing from positive to negative edge selection on PA[0] will
immediately trigger an IRQPA[0] if the IRQ was not masked.


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