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EM6617 Datasheet(PDF) 11 Page - EM Microelectronic - MARIN SA |
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EM6617 Datasheet(HTML) 11 Page - EM Microelectronic - MARIN SA |
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11 / 65 page 
EM6617 Copyright © 2005, EM Microelectronic-Marin SA 11 www.emmicroelectronic.com Table 5.4.1 Watchdog Timer Register RegSysCntl2 Bit Name Reset R/W Description 3 WDReset 0 R/W Reset the Watchdog 1 -> Resets the Logic Watchdog 0 -> No action The Read value is always '0' 2 SleepEn 0 R/W See Operating modes (sleep) 1 WDVal1 0 R Watchdog timer data Ck[1] divided by 4 0 WDVal0 0 R Watchdog timer data Ck[1] divided by 2 Table 5.4.2 Watchdog Control Register RegSysCntl3 Bit Name Reset R/W Description 3 Vref1/2Sel 0 R/W Reference selection for the ADC 2 -- 0 R/W always reads 0 1 NoOscWD 0 R/W No oscillation supervisor 0 NoLogicWD 0 R/W No logic watchdog 5.5 CPU State after Reset Reset initializes the CPU as shown in Table 5.5.1 below. Table 5.5.1 Initial CPU Value after Reset. Name Bits Symbol Initial Value Program counter 0 12 PC0 hex 000 (as a result of Jump 0) Program counter 1 12 PC1 Undefined Program counter 2 12 PC2 Undefined Stack pointer 2 SP PSP[0] selected Index register 7 IX Undefined Carry flag 1 CY Undefined Zero flag 1 Z Undefined Halt 1 HALT 0 Instruction register 16 IR Jump 0 Periphery registers 4 Reg. See peripheral memory map |
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