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EM6617 Datasheet(PDF) 8 Page - EM Microelectronic - MARIN SA

Part No. EM6617
Description  Ultra Low Power Microcontroller with ADC AND EEPROM
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Maker  EMMICRO [EM Microelectronic - MARIN SA]
Homepage  http://www.emmicroelectronic.com
Logo EMMICRO - EM Microelectronic - MARIN SA

EM6617 Datasheet(HTML) 8 Page - EM Microelectronic - MARIN SA

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EM6617
Copyright
© 2005, EM Microelectronic-Marin SA
8
www.emmicroelectronic.com
5. Reset
Figure 8. illustrates the reset structure of the EM6617-1. There are six possible reset sources :
(1) Internal initial reset from the Power On Reset (POR) circuitry.
--> POR
(2) External reset from the Reset terminal.
--> System Reset, Reset CPU
(3) External reset by simultaneous high/low inputs to port A.
--> System Reset, Reset CPU
(Combinations are defined in the registers
OptInpRSel1 and OptInpRSel2)
(4) Internal reset from the Digital Watchdog.
--> System Reset, Reset CPU
(5) Internal reset from the Oscillation Detection Circuit.
--> System Reset, Reset CPU
(6) Internal reset when sleep mode is activated.
--> System Reset, Reset
CPU
All reset sources activate the System Reset and the Reset CPU. The ‘System Reset Delay’ ensures that the
system reset remains active long enough for all system functions to be reset (active for n system clock cycles).
The ‘CPU Reset Delay’ ensures that the reset CPU remains active until the oscillator is in stable oscillation.
As well as activating the system reset and the reset CPU, the POR also resets all option registers and the sleep
enable (
SleepEn) latch. System reset and reset CPU do not reset the option registers nor the SleepEn latch.
Reset state can be shown on Strobe terminal by selecting
StrobeOutSel1,0 = 0 in OPTCandStr register.
Figure 8. Reset Structure
Sy s te m R e s e t
De la y
CP U Re s e t
De la y
En a b le
A c tiv a te
Dig it a l
W a tc h dog
O s c illa tio n
De te c tio n
R e s e t f r o m P o r t A
In p u t C o m b in a tio n
Re s e t P A D
Sle e p
O p tInp R S le ep
Re s e t
CP U
In hibit
O s c illa tio n
De te c tio n
In h ib it
Dig ita l
W a tc hd og
PO R
P O R to O p tio n
R e g is ter s & S lee pE n
La tc h
DE B O UNCE
Sle e p
La tc h
S lee pE n
Latc h
PO R
In te r n a l D a ta B u s
Wr ite R e s e t
R e ad S ta tus
Wr ite A c tiv e
R e a d S tatus
C k [10]
Ck [1 ]
Ck [8 ]
Ck [1 ]
Ck [ 1 5 ]
PO R
A n alog ue
Filte r


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