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EM6617 Datasheet(PDF) 36 Page - EM Microelectronic - MARIN SA |
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EM6617 Datasheet(HTML) 36 Page - EM Microelectronic - MARIN SA |
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36 / 65 page 
EM6617 Copyright © 2005, EM Microelectronic-Marin SA 36 www.emmicroelectronic.com 11. EEPROM ( 64 × 8 Bit ) The EEPROM addressing is indirect using 6 bits (64 addresses) defined in RegEEPAdr and RegEEPCntl registers. The EEPROM consist of 2 pages 32x8bit each, address EEPAdr[4 :0]. The page is selected in the RegEEPCntl register bit EEPage. So the user can address the EEPROM as it would be one block of 64x8 bit. Any access to the EEPROM is done in two phases. 1 st, one needs to define the address location. 2nd, one needs to start the desired action, read or write. Refer to the examples below.. How to read data from EEPROM : 1 st inst. : write EEPROM address (4 low bits) in RegEEPAddr register. 2 nd inst. : write the high address bit, page and select reading operation in RegEEPCntl. ( EEPAdr[4], EEPage, EEPRdWr=0) 3 rd inst. : NOP instruction in case of 128kHz operation (metal option setting). 4 th inst. : read EEPROM low data in RegEEPDataL register. 5 th inst. : read EEPROM high data in RegEEPDataH register. The two last instructions can be executed in the reverse order. How to write data in EEPROM : 1 st inst. : write EEPROM address (4 low bits) in RegEEPAdr register. 2 nd inst. : write EEPROM low data in RegEEPDataL register. 3 rd inst.: write EEPROM high data in RegEEPDataH register. 4 th inst. : write the high address bit, page and select writing operation in RegEEPCntl. ( EEPAdr[4], EEPage, EEPRdWr=1) 5 th . : IRQEEP is generated at the end of write. The three first instructions can be executed in any order. Writing RegEEPCntl register starts automatically EEPROM reading or writing operation according to the bit EEPRdWr. EEPROM access time is max. 20µs : Data is available in RegEEPDataL and RegEEPDataH registers at the instruction following the read access on 32kHz system clock The read signal is 1.5 system clock wide. The CPU reads at end of phase 3. With the 128kHz metal option the EERead signal is 3.5 system clock cycles wide. Using this option the user must use a NOP instruction before actually reading the RegEEPDataL,H values. EEPROM writing operation lasts 24ms (Erase followed by write). The flag EEPBusy in RegEEPCntl register stays high until the writing operation is finished. An interrupt request IRQEEP is generated at the end of each writing operation. While EEPBusy is high the EEPROM must not be used at all. The EEPROM interrupt request can be masked (default) ( MaskIRQEEP bit). See also the interrupt handling section 13 for further information . Note : Any Reset or sleep mode will immediately cancel the EEPROM write operation. The data to be stored at this time may be corrupted. Figure 27. Read Timing 32kHz operation Max. 20 µs EE Read EE Stable Data Sys. Clock CPU Phase 4 3 2 1 4 3 1 2 |
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