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SDA9410-B13 Datasheet(PDF) 20 Page - Micronas

Part No. SDA9410-B13
Description  Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
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Maker  MICRONAS [Micronas]
Homepage  http://www.micronas.com
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SDA9410-B13 Datasheet(HTML) 20 Page - Micronas

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SDA9410
Preliminary Data Sheet
Introduction
20
Micronas
For this usage the 6 Mbit eDRAM core is separated in two luminance fields and two
chrominance fields (either 4:2:0 or 4:1:1) and a memory area for luminance and
chrominance fields (4:1:1) [maximum circa 1/9 picture] for picture-in-picture applications.
The vector based scan rate conversion is possible for the master channel only.
For the SSC mode the 6 Mbit eDRAM core is split in two 3 Mbit areas, which are able to
contain a maximum of two luminance fields and two chrominance fields (either 4:2:0 or
4:1:1). The figure below shows different applications (“Double window”, “Zoom-in-zoom-
out”). In this case only a simple scan rate conversion (e.g. field doubling for interlaced
conversion: AABB) for both output channels is possible.
Figure 5
Principles of SSC mode


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