 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SDA9410-B13 Datasheet(PDF) 20 Page - Micronas |
|
||||||||||||||||||||||||||||||
SDA9410-B13 Datasheet(HTML) 20 Page - Micronas |
|
|
20 / 179 page 
SDA9410 Preliminary Data Sheet Introduction 20 Micronas For this usage the 6 Mbit eDRAM core is separated in two luminance fields and two chrominance fields (either 4:2:0 or 4:1:1) and a memory area for luminance and chrominance fields (4:1:1) [maximum circa 1/9 picture] for picture-in-picture applications. The vector based scan rate conversion is possible for the master channel only. For the SSC mode the 6 Mbit eDRAM core is split in two 3 Mbit areas, which are able to contain a maximum of two luminance fields and two chrominance fields (either 4:2:0 or 4:1:1). The figure below shows different applications (“Double window”, “Zoom-in-zoom- out”). In this case only a simple scan rate conversion (e.g. field doubling for interlaced conversion: AABB) for both output channels is possible. Figure 5 Principles of SSC mode |
English ▼
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
