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SDA9410-B13 Datasheet(PDF) 17 Page - Micronas

Part No. SDA9410-B13
Description  Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
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Maker  MICRONAS [Micronas]
Homepage  http://www.micronas.com
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SDA9410-B13 Datasheet(HTML) 17 Page - Micronas

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SDA9410
Preliminary Data Sheet
Pin Description
17
Micronas
Table 1
Pin definitions and functions
Symbol
Pin
Num.
Input
Outp.
Function
VSSLx *)
8,13,15,16,
22,23,75
S
Supply voltage for digital logic parts (
V
SS = 0 V )
VDDLx
9,12, 68,74
S
Supply voltage for digital logic parts ( VDD = 3.3 V )
VSSPx
10,17,29,43,
57, 70, 79,
100
S
Supply voltage for pads ( VSS = 0 V )
VDDPx
11,21,36,54,
69, 80,99
S
Supply voltage for pads ( VDD = 3.3 V )
VSSE1
67
S
Supply voltage for embedded DRAM ( VSS = 0 V )
VDDEx
14,66
S
Supply voltage for embedded DRAM ( VDD = 3.3 V )
VSSAx
19,59,92,96,
98
S
Supply voltage for analog PLL and for analog parts DAC ( VSS = 0 V )
VDDAx
20,60, 95,97
S
Supply voltage for analog PLL and for analog parts DAC
( VDD = 3.3 V )
YINM 0...7
39,...,42;
44,...,47
I/TTL
Data input Y master channel
UVINM 0...7
30,...,35;
37; 38
I/TTL PD Data input UV master channel
YINS 0...7
61,...,65;
71,...,73
I/TTL PD Data input Y slave channel
UVINS 0...7
48,..,53;
55;56
I/TTL PD Data input UV slave channel
RESET
81
I/TTL
System reset. The RESET input is low active. In order to ensure
correct operation a "Power On Reset" must be performed. The
RESET pulse must have a minimum duration of two clock periods of
the master (CLKM) and slave clock (CLKS), respectively.
HINM
27
I/TTL
PD
H-Sync input master channel
VINM
26
I/TTL
PD
V-Sync input master channel
SYNCENM
28
I/TTL
Synchronization enable input master channel
HINS
77
I/TTL
PD
H-Sync input slave channel
VINS
78
I/TTL
PD
V-Sync input slave channel
SYNCENS
76
I/TTL
Synchronization enable input slave channel
SDA
24
IO
I2C-Bus data line
SCL
25
I
I2C-Bus clock line
BLANK
7
O/TTL
Blanking signal
VOUT
5
O/TTL
V-Sync output
HOUT
4
O/TTL
H-Sync output


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