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SDA9410-B13 Datasheet(PDF) 13 Page - Micronas |
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SDA9410-B13 Datasheet(HTML) 13 Page - Micronas |
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13 / 179 page 
SDA9410 Preliminary Data Sheet Features 13 Micronas converter - 36 kbit SRAM for block matching, line-to-block converter • Flexible clock and synchronization concept - Decoupling of the input and output clock system possible • Scan rate conversion - Motion compensated 100/120 Hz interlaced scan conversion (Micronas VDU) - Motion compensated 50/60 Hz progressive scan conversion (Micronas VDU) - Simple interlaced modes: ABAB, AABB, AAAA, BBBB - Simple progressive modes: AB, AA*, B*B - True Motion: 50 Hz motion resolution even for 25 Hz PAL film sources 60 Hz motion resolution even for 30 Hz NTSC film sources - Large area and line flicker reduction • Flexible digital vertical expansion of the output signal (1.0, ... [1/64] ... , 2.0) • Sharpness improvement - Digital colour transition improvement (DCTI) - Digital luminance transition improvement (DLTI) - Peaking (luminance only) • Flexible output sync controller - Flexible positioning of the two output channels in all application modes - Flexible height and width of the two output pictures - Flexible programming of the output sync raster • Signal manipulations - Still frame or field - Insertion of coloured background - Insertion of a selection border - Adjustable delay between Y and UV signal (+4,...[1]...,-3 input pixels) at the input side - Adjustable delay between Y and UV signal (+3,...[0.5]...,- 4 output pixels) at the output side • Three D/A converters - 9 bit amplitude resolution for Y, -(R-Y), -(B-Y) output - 60 MHz maximal clock frequency - Two-fold oversampling - Simplification of external analog post filtering and differential analog outputs • I²C-bus control (400 kHz) • P-MQFP-100 package • 3.3 V ± 5% supply voltage |
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