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SDA9410-B13 Datasheet(PDF) 78 Page - Micronas

Part No. SDA9410-B13
Description  Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
Download  179 Pages
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Maker  MICRONAS [Micronas]
Homepage  http://www.micronas.com
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SDA9410-B13 Datasheet(HTML) 78 Page - Micronas

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SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S)
78
Micronas
1: Background channel
2: Output channel master
3: Output channel slave
The background channel has always the lowest priority. The priority between output
channel master and slave is defined by an I²C Bus parameter PRIORMS. The figure
below shows an example for the combination of the three channels. The background
colour black has lowest priority. The picture content of master channel is a phone and
the picture content of slave channel is a airplane. In this case the slave channel has the
highest priority. To enable or disable the display of the master or slave channel the I²C
parameters MASTERON and SLAVEON can be used.
Figure 35
Output I²C Bus parameter
4*LPFOP+1
(PPLOP*2)*CLKD
(NALOPD+1)*2
ALPFOPD*8
(APPLOPD*8)*CLKD
(NAPOPD*4)*CLKD
HOUT
VOUT
(HORPOSM*4)*CLKD
(HORPOSS*4)*CLKD
(HORWIDTHS*4)*CLKD
VERPOSS
VERPOSM
VERWIDTHM*8
VERWIDTHS*4
(HORWIDTHM*8)*CLKD
BLANK
(BLANLEN*8)*CLKD
((6 MSBs of BLANDEL)*8 + (2
LSBs of BLANDEL))*CLKD


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