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SDA9410-B13 Datasheet(PDF) 53 Page - Micronas

Part No. SDA9410-B13
Description  Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
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Maker  MICRONAS [Micronas]
Homepage  http://www.micronas.com
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SDA9410-B13 Datasheet(HTML) 53 Page - Micronas

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SDA9410
Preliminary Data Sheet
Application modes and memory concept
53
Micronas
Table 36
Input write I²C Bus parameter
5.6
Application modes and memory concept
5.6.1
Introduction
The Main Memory of the SDA 9410 has an overall capacity of 6 Mbit. It is divided into
two identical and independent 3 Mbit parts.
The Main Memory has 2 completely independent data inputs (master and slave channel)
to enable a multitude of PIP features. In general the channels are asynchronous having
2 separate clock PLLs (CLKM, CLKS). Reading of master and slave data for display is
performed using a third asynchronous clock (CLKD). In this way a decoupling of input
and output clocks is achieved.
The Main Memory supports different operation modes of the SDA 9410 by adapted data
configurations. The different modes are defined by the I²C Bus parameter MEMOP (I²C
Bus sub address 53h).
I²C Bus
parameter
Sub address
Description
PLLMOFF
1: off
0: on
00h
PLLM master channel on or off, only for test purpose
PLLMRA
00h
PLLM range, only for test purpose
PLLSOFF
1: off
0: on
22h
PLLS slave channel on or off, only for test purpose
PLLSRA
22h
PLLS range
PLLDOFF
1: off
0: on
5Fh
PLLD display channel on or off, only for test purpose
PLLDRA
5Fh
PLLD range
CLKOUTON
1: enabled
0: disabled
5Fh
Output of system clock CLKOUT
CLKMDEN
1: X1/CLKD
0: CLKM
5Fh
Input clock for PLLD


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