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EDI88512CAXN36I Datasheet(PDF) 1 Page - White Electronic Designs Corporation |
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EDI88512CAXN36I Datasheet(HTML) 1 Page - White Electronic Designs Corporation |
1 / 9 page EDI88512CA 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs October 2004 Rev. 11 White Electronic Designs Corp. reserves the right to change products or specifications without notice. 512Kx8 Monolithic SRAM, SMD 5962-95600 FEATURES Access Times of 15, 17, 20, 25, 35, 45, 55ns Data Retention Function (LPA version) TTL Compatible Inputs and Outputs Fully Static, No Clocks Organized as 512Kx8 Commercial, Industrial and Military Temperature Ranges 32 lead JEDEC Approved Evolutionary Pinout • Ceramic Sidebrazed 600 mil DIP (Package 9) • Ceramic Sidebrazed 400 mil DIP (Package 326) • Ceramic 32 pin Flatpack (Package 344) • Ceramic Thin Flatpack (Package 321) • Ceramic SOJ (Package 140) 36 lead JEDEC Approved Revolutionary Pinout • Ceramic Flatpack (Package 316) • Ceramic SOJ (Package 327) • Ceramic LCC (Package 502) Single +5V (±10%) Supply Operation The EDI88512CA is a 4 megabit Monolithic CMOS Static RAM. The 32 pin DIP pinout adheres to the JEDEC evolutionary standard for the four megabit device. All 32 pin packages are pin for pin upgrades for the single chip enable 128K x 8, the EDI88128CS. Pins 1 and 30 become the higher order addresses. The 36 pin revolutionary pinout also adheres to the JEDEC standard for the four megabit device. The center pin power and ground pins help to reduce noise in high performance systems. The 36 pin pinout also allows the user an upgrade path to the future 2Mx8. A Low Power version with Data Retention (EDI88512LPA) is also available for battery backed applications. Military product is available compliant to Appendix A of MIL- PRF-38535. *This product is subject to change without notice. 36 PIN TOP VIEW PIN DESCRIPTION I/O0-7 Data Inputs/Outputs A0-18 Address Inputs WE# Write Enables CS# Chip Selects OE# Output Enable VCC Power (+5V ±10%) VSS Ground NC Not Connected BLOCK DIAGRAM Memory Array Address Buffer Address Decoder I/O Circuits A0-18 I/O0-7 WE# CS# OE# FIG. 1 PIN CONFIGURATION 32 PIN TOP VIEW NC A18 A17 A16 A15 OE# I/O7 I/O6 Vss Vcc I/O5 I/O4 A14 A13 A12 A11 A10 NC 36 pin Revolutionary A0 A1 A2 A3 A4 CS# I/O0 I/O1 Vcc Vss I/O2 I/O3 WE# A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 32 pin Evolutionary A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc A15 A17 WE# A13 A8 A9 A11 OE# A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3 |
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