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EDI88512CXCI Datasheet(PDF) 1 Page - White Electronic Designs Corporation |
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EDI88512CXCI Datasheet(HTML) 1 Page - White Electronic Designs Corporation |
1 / 7 page EDI88512C 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs February 2001 Rev. 11 White Electronic Designs Corp. reserves the right to change products or specifications without notice. 512Kx8 Monolithic SRAM, CMOS The EDI88512C is a 4 megabit Monolithic CMOS Static RAM. The 32 pin DIP pinout adheres to the JEDEC evolutionary standard for the four megabit device. Both the DIP and CSOJ packages are pin for pin upgrades for the single chip enable 128K x 8, the EDI88128C. Pins 1 and 30 become the higher order addresses. A Low Power version with Data Retention (EDI88512LP) is also available for battery backed applications. Military product is available compliant to Appendix A of MIL-PRF- 38535. * This product is subject to change without notice. PIN DESCRIPTION I/O0-7 Data Inputs/Outputs A0-18 Address Inputs WE# Write Enables CS# Chip Selects OE# Output Enable VCC Power (+5V ±10%) VSS Ground NC Not Connected BLOCK DIAGRAM Memory Array Address Buffer Address Decoder I/O Circuits A0-18 I/O0-7 WE# CS# OE# FIGURE 1 – PIN CONFIGURATION 32 PIN TOP VIEW 32 pin Evolutionary A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc A15 A17 WE# A13 A8 A9 A11 OE# A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3 FEATURES 512Kx8 bit CMOS Static Random Access Memory • Access Times of 70, 85, 100ns • Data Retention Function (LP version) • TTL Compatible Inputs and Outputs • Fully Static, No Clocks 32 lead JEDEC Approved Evolutionary Pinout • Ceramic Sidebrazed 600 mil DIP (Package 9) • Ceramic SOJ (Package 140) Single +5V (±10%) Supply Operation |
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