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EDI88128LPSXCB Datasheet(PDF) 3 Page - White Electronic Designs Corporation |
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EDI88128LPSXCB Datasheet(HTML) 3 Page - White Electronic Designs Corporation |
3 / 9 page 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs EDI88128CS February 2000 Rev. 10 White Electronic Designs Corp. reserves the right to change products or specifications without notice. 30pF 480Ω Vcc Q Figure 1 Figure 2 255Ω 5pF 480Ω Vcc Q 255Ω AC TEST CONDITIONS AC CHARACTERISTICS – READ CYCLE (15 to 20ns) VCC = 5.0V, Vss = 0V, -55°C ≤ TA ≤ +125°C Parameter Symbol 15ns* 17ns 20ns Units JEDEC Alt. Min Max Min Max Min Max Read Cycle Time tAVAV tRC 15 17 20 ns Address Access Time tAVQV tAA 15 17 20 ns Chip Enable Access Time tELQV tACS 15 17 20 ns Chip Enable to Output in Low Z (1) tELQX tCLZ 333 ns Chip Disable to Output in High Z (1) tEHQZ tCHZ 8 8 10 ns Output Hold from Address Change tAVQX tOH 000 ns Output Enable to Output Valid tGLQV tOE 668 ns Output Enable to Output in Low Z (1) tGLQX tOLZ 000 ns Output Disable to Output in High Z(1) tGHQZ tOHZ 668 ns Chip Enable to Power Up (1) tELICCH tPU 000 ns Chip Enable to Power Down (1) tEHICCL tPD 15 17 20 ns 1. This parameter is guaranteed by design but not tested. AC CHARACTERISTICS – READ CYCLE (25 to 55ns) VCC = 5.0V, Vss = 0V, -55°C ≤ TA ≤ +125°C Symbol 25ns 35ns 45ns 55ns Parameter JEDEC Alt. Min Max Min Max Min Max Min Max Units Read Cycle Time tAVAV tRC 25 35 45 55 ns Address Access Time tAVQV tAA 25 35 45 55 ns Chip Enable Access Time tELQV tACS 25 35 45 55 ns Chip Enable to Output in Low Z (1) tELQX tCLZ 3333 ns Chip Disable to Output in High Z (1) tEHQZ tCHZ 12 20 20 20 ns Output Hold from Address Change tAVQX tOH 0000 ns Output Enable to Output Valid tGLQV tOE 10 15 20 25 ns Output Enable to Output in Low Z (1) tGLQX tOLZ 0000 ns Output Disable to Output in High Z(1) tGHQZ tOHZ 10 15 20 20 ns Chip Enable to Power Up (1) tELICCH tPU 0000 ns Chip Enable to Power Down (1) tEHICCL tPD 25 35 45 55 ns 1. This parameter is guaranteed by design but not tested. Input Pulse Levels VSS to 3.0V Input Rise and Fall Times 5ns Input and Output Timing Levels 1.5V Output Load Figure 1 NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2 |
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