NexFlash Technologies, Inc.
1
NXPF001F-0600
06/22/00 ©
This document contains PRELIMINARY data. NexFlash reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We
assume no responsibility for any errors which may appear in this publication. © Copyright 1998, NexFlash Technologies, Inc..
NX29F010
1M-BIT (128K x 8-bit)
CMOS, 5.0V Only
ULTRA-FAST SECTORED FLASH MEMORY
FEATURES
• Ultra-fast Performance
– 35, 45, 55, 70, and 90 ns max. access times
• Temperature Ranges
– Commercial 0
oc-70oc
– Industrial -40
oc-85oc
• Single 5V-only Power Supply
– 5V ± 10% for Read, Program, and Erase
• CMOS Low Power Consumption
– 20 mA (typical) active read current
– 30 mA (typical) Program/Erase current
• Compatible with JEDEC-Standard Pinouts
– 32-pin DIP, PLCC, TSOP
• Program/function Compatible with AM29F010
– No system firmware changes
– Uses same PROM programer algorithm
• Flexible sector architecture
– Erase any of eight uniform sectors or full chip erase
– Sector protection/unprotection using PROM
programming equipment
• 100,000 Program/Erase cycles
• Embedded algorithms
– Automatically programs and verifies data at
specified address
– Auto-programs and erases the chip or any
designated sector
• Data/Polling and Toggle Bits
– Detect program or erase cycle completion
JUNE 2000
DESCRIPTION
The
NexFlash NX29F010 is a 1 Megabit (131,072 bytes)
single 5.0V-only Sectored Flash Memory. The NX29F010
provides in-system programming with the standard system
5.0V-only Vcc supply and can be programmed or erased in
standard PROM programmers.
The NX29F010 offers access times of 35, 45, 55, 70, and
90 ns allowing high-speed controller and DSPs' to operate
without wait states. Byte-wide data appears on DQ0-DQ7.
Separate chip enable (
CE), write enable (WE), and output
enable (
OE) controls eliminates bus contention.
Power consumption is greatly reduced when the system
places the device into the Standby Mode.
The device is offered in 32-pin PLCC, TSOP, and PDIP
packages.
Principles of Operation
Only a single 5.0V power supply is required for both read and
write functions. Program or erase operations do not require
12.0V VPP. Internally generated and regulated voltages are
provided for the program and erase operations.
The device is entirely command set compatible with the
JEDEC single power supply Flash standard. Commands
are written to the command register using standard micro-
processor write timings. Register contents serve as input to
an internal state machine that controls the erase and
programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and
erase operations. Reading data out of the device is similar
to reading from other Flash or EPROM devices.
Executing the Program Command Sequence invokes the
Embedded Program Algorithm, an internal algorithm that
automatically times the program pulse widths and verifies
proper cell margin.
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