Copyright

 2002, EM Microelectronic-Marin SA

3

www.emmicroelectronic.com

EM4022

Absolute Maximum Ratings

Parameter

Symbol

Conditions

Maximum AC peak current

induced on COIL1 and

COIL2

± 30 mA

Maximum DC voltage

(note1)

5 V

Maximum DC current

supplied into M

(note1)

60 mA

Power supply

Max. voltage other pads

Min. voltage other pads

Storage temperature

-55 to +125

Electrostatic discharge

maximum to MIL-STD-883C

method 3015

1000 V

note1) whatever is reached first

Stresses above these listed maximum ratings may cause

permanent damage to the device. Exposure beyond

specified operating conditions may affect device

reliability or cause malfunction.

Handling Procedures

This device has built-in protection against high static

voltages or electric fields; however, due to the unique

properties of this device, anti-static precautions should

be taken as for any other CMOS component. Unless

otherwise specified, proper operation can only occur

when all the terminal voltages are kept within the supply

voltage range.

Operating Conditions

Parameter

Symbol Min Typ Max Units

-40

+85

Maximum coil current

-10

10

mA

AC voltage on coil*

15

DC voltage on M*

3.5

V

* The AC voltage on the coil and the DC voltage at pad

M are limited by the on-chip shunt regulator loaded at

Electrical Characteristics

Parameter

Symbol Test conditions

Min

Typ

Max Units

V

Regulated voltage

3.3

4

4.7

V

Oscillator frequency

92

125

160

kHz

Power-on reset threshold

0.9

1.4

1.8

V

Power-on reset threshold

0.7

1.2

1.6

V

Power-on reset hysteresis

80

160

240

mV

GAP input time constant

Extrapolated with an external

capacitor of 64nF

0.4

µs

Modulation transistor ON resistance

48

Ω

Resonance capacitor

f = 100KHz, 100mVpp

106.7

110 113.3

pF

Supply capacitor

f = 100KHz, 100mVpp

140

pF

69

13

µA

Shunt Regulator current consumption

200

500

nA

Gap pull-up current consumption

1.8

5

7

µA

Dynamic current consumption

3.5

5

6.5

µA

Timing Characteristics

1) All timings are derived from the on-chip oscillator.

2) The minimum low frequency GAP width for a single chip is 1 bit at its own clock frequency. The reader must however

allow for the spread in clock frequencies possible in a group of tags. Therefore the minimum width of the GAP in MUTE

and WAKE-UP signals must be 1.5 bits. High frequency GAPs can be arbitrarily.

3) The maximum GAP width for a single chip is 6 bits at its own clock frequency. The reader must however allow for the

spread in clock frequencies possible in a group of tags. Therefore the maximum width of the GAP in MUTE and WAKE-UP

signals must be 5 bits.

Parameter

Symbol Test conditions

Min

Typ

Max Units

High frequency GAP width

50

ns

High frequency ACK GAP width

6bit

High frequency MUTE and WAKE-UP GAP width

5bit

Low frequency ACK GAP width

1.0

2

6

bit

Low frequency MUTE and WAKE-UP GAP width

1.5

2

5

bit

GAP separation in WAKE-UP signal

1.5

2

5

bit