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74F569 Datasheet(PDF) 3 Page - NXP Semiconductors

Part No. 74F569
Description  4-bit bidirectional binary synchronous counter 3-State
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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74F569 Datasheet(HTML) 3 Page - NXP Semiconductors

 
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Philips Semiconductors
Product specification
74F569
4-bit bidirectional binary synchronous counter (3-State)
1996 Jan 05
3
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0 - D3
Parallel data inputs
1.0/1.0
20
µA/0.6mA
CEP
Count Enable parallel input (active Low)
1.0/1.0
20
µA/0.6mA
CET
Count Enable Trickle input (active Low)
1.0/2.0
20
µA/1.2mA
CP
Clock input (active rising edge)
1.0/1.0
20
µA/0.6mA
PE
Parallel Enable input (active Low)
1.0/2.0
20
µA/1.2mA
U/D
Up/Down count control input
1.0/1.0
20
µA/0.6mA
OE
Output Enable input
1.0/1.0
20
µA/0.6mA
MR
Master Reset input (active Low)
1.0/1.0
20
µA/0.6mA
SR
Synchronous Reset (active Low)
1.0/1.0
20
µA/0.6mA
TC
Terminal count output (active Low)
50/33
1.0mA/20mA
CC
Clocked carry output (active Low)
50/33
1.0mA/20mA
Q0 - Q3
Data outputs
150/40
3.0mA/24mA
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20
µA in the High state and 0.6mA in the Low state.
FUNCTIONAL DESCRIPTION
The 74F569 counts in the modulo-16 binary sequence. From
state 0 (LLLL) it will increment to 15 in the up mode; in the down
mode it will decrement from 15 to 0. The clock inputs of all flip-flops
are driven parallel through a clock buffer. All state changes (except
due to Master Reset) occur synchronously with the Low-to-High
transition of the Clock Pulse (CP) input.
The circuit has five fundamental modes of operation, in order of
precedence: asynchronous reset, synchronous reset, parallel load,
count and hold. Six control inputs–Master Reset (MR), Synchronous
Reset (SR), Count Enable Trickle (CET), Parallel Enable (PE),
Count Enable Parallel (CEP), and the Up/Down (U/D) input –
determine the mode of operation, as shown in the Function Table.
A Low signal on MR overrides all other inputs and asynchronously
forces the flip-flop Q outputs Low. A Low signal on SR overrides
counting and parallel loading and allows the Q output to go Low on
the next rising edge of CP. A Low signal on PE overrides counting
and allows information on the parallel data (Dn) inputs to be loaded
into the flip-flops on the next rising edge of CP. With MR, SR, and
PE High, CEP and CET permit counting when both are Low.
Conversely, a High signal on either CEP and CET inhibits counting.
The 74F569 uses edge-triggered flip-flops and changing the SR, PE,
CEP, CET or U/D inputs when the CP is in either state does not
cause errors, provided that the recommended setup and hold times,
with respect to the rising edge of CP, are observed. Two types of
outputs are provided as overflow/underflow indicators. The Terminal
Count (TC) output is normally High and goes Low provided CET is
Low, when the counter reaches zero in the down mode, or reaches
maximum 15 in the up mode
TC will then remain Low until a state change occurs by counting or
presetting, or until U/D or CET is changed.
To implement synchronous multistage counters, the connections
between the TC output and the CEP and CET inputs can provide
either slow or fast carry propagation. Figure 1 shows the
connections for a simple ripple carry, in which the clock period must
be longer than the CP to TC delay of the first stage, plus the
cumulative CET to TC delays of the intermediate stages, plus the
CET to CP setup time of the last stage. This total delay plus setup
time sets the upper limit on clock frequency. For faster clock rates,
the carry look ahead connections in Figure 2 are recommended. In
this scheme the ripple delay through the intermediate stages
commences with the same clock that causes the first stage to tick
over from Max to Min in the up mode, or Min to Max in the down
mode, to start its final cycle. Since this takes 16 clocks to complete,
there is plenty of time for the ripple to progress through the
intermediate stages. The critical timing that limits the clock period is
the CP to TC delay of the first stage plus the CEP to CP setup time
of the last stage. The TC output is subject to decoding spikes due to
internal race conditions and is therefore not recommended for use
as a clock or asynchronous reset for flip-flops, register or counters.
For such applications, the Clocked Carry (CC) output is provided.
The CC output is normally High. When CEP, CET, and TC are Low,
the CC output will go Low, when the clock next goes Low and will
stay Low until the clock goes High again; as shown in the CC
Function Table. When the Output Enable (OE) is Low, the parallel
data outputs Q0–Q3 are active and follow the flip-flop Q outputs. A
High signal on OE forces Q0–Q3 to the High impedance state but
does not prevent counting, loading or resetting.
LOGIC EQUATIONS:
Count Enable=CEP
×CET×PE
Up: TC=Q0
×Q1×Q2×Q3×(Up)×CET
Down: TC=Q0
×Q1×Q2×Q3×(Down)×CET


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