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TVP5040 Datasheet(PDF) 90 Page - Texas Instruments

Part No. TVP5040
Description  NTSC/PAL Digital Video Decoder With Macrovision Detection
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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2–74
2.13.62 FIFO Control
VIP address
1B6h
PHI address
B6h
I2C address
B6h
7
6
5
4
3
2
1
0
Reserved
CCD reset
Read in Progress
RAM Test
TTX PHI Output Enable
FIFO Reset
CCD reset
When a 1 is written to this register bit, the closed caption register is reset. Also, the flag is
cleared to 0. This bit is automatically cleared back to 0.
Read in progress
This bit indicates that the first byte of a teletext transaction has been read, but the last byte
has not been read. This bit can be used to verify data alignment as it is read from the FIFO.
RAM test
Setting this bit high allows the external processor to write data into the FIFO. In this mode,
data from the TXP is ignored. This allows the micro to test the RAM by writing and reading
test patterns. The default value is zero.
TTX PHI output enable
A 1 in this register enables access to the teletext data in the FIFO through the parallel host
port or I2C interface and disables access from the output formatter. A 0 disables access
from the parallel host port or I2C interface and enables access from the output formatter.
The default value is one.
FIFO reset
When a 1 is written to this register bit, the FIFO is flushed. This is done by clearing the read
and write pointers to zero, clearing the Tx count to zero, and clearing all status flags. This
bit is automatically cleared back to 0.
2.13.63 FIFO RAM Test
VIP address
1B7h
PHI address
B7h
I2C address
B7h
7
6
5
4
3
2
1
0
FIFO RAM Data
FIFO RAM test register provides diagnostic capability into the internal teletext FIFO. This register can be written
sequentially with a block of data. The data is read back using the teletext FIFO data register at address B0h to verify
the correct operation of the FIFO.




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