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N74F5074N Datasheet(PDF) 7 Page - NXP Semiconductors |
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N74F5074N Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 12 page Philips Semiconductors Product specification 74F5074 Synchronizing dual D-type flip-flop/clock driver September 14, 1990 7 AC ELECTRICAL CHARACTERISTICS LIMITS Tamb = +25°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT CONDITION CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω MIN TYP MAX MIN MAX fmax Maximum clock frequency Waveform 1 105 120 90 ns tPLH tPHL Propagation delay CPn to Qn or Qn Waveform 1 2.0 2.0 3.9 3.9 6.0 6.0 1.5 2.0 6.5 6.5 ns tPLH tPHL Propagation delay SDn, RDn to Qn or Qn Waveform 2 3.0 3.0 4.5 5.0 7.5 7.5 2.5 2.5 8.0 8.0 ns tsk(o) Output skew1,2 Waveform 4 1.5 1.5 ns NOTES: 1. |tPN actual – tPM actual| for any output compared to any other output where N and M are either LH or HL. 2. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.,). AC SETUP REQUIREMENTS LIMITS Tamb = +25°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT CONDITION CL = 50pF, RL = 500Ω CL = 50pF, RL = 500Ω MIN TYP MAX MIN MAX tsu (H) tsu(L) Setup time, high or low Dn to CPn Waveform 1 1.5 1.5 2.0 2.0 ns th (H) th (L) Hold time, high or low Dn to CPn Waveform 1 1.0 1.0 1.5 1.5 ns tw (H) tw (L) CPn pulse width, high or low Waveform 1 3.0 4.0 3.0 4.5 ns tw (L) SDn or RDn pulse width, low Waveform 2 3.0 4.0 ns trec Recovery time SDn or RDn to CPn Waveform 3 3.0 3.5 ns |
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