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IDT74ALVCH16721 Datasheet(PDF) 2 Page - Integrated Device Technology

Part No. IDT74ALVCH16721
Description  3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT74ALVCH16721 Datasheet(HTML) 2 Page - Integrated Device Technology

   
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INDUSTRIALTEMPERATURERANGE
2
IDT74ALVCH16721
3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
SSOP/ TSSOP
TOP VIEW
PIN CONFIGURATION
Symbol
Description
Max
Unit
VTERM(2) Terminal Voltage with Respect to GND
–0.5 to +4.6
V
VTERM(3) Terminal Voltage with Respect to GND
–0.5 to VCC+0.5
V
TSTG
Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–50 to +50
mA
IIK
Continuous Clamp Current,
±50
mA
VI < 0 or VI > VCC
IOK
Continuous Clamp Current, VO < 0
–50
mA
ICC
Continuous Current through each
±100
mA
ISS
VCC or GND
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
NOTE:
1. As applicable to the device type.
Symbol
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
5
7
pF
COUT
Output Capacitance
VOUT = 0V
7
9
pF
CI/O
I/O Port Capacitance
VIN = 0V
7
9
pF
CAPACITANCE (TA= +25°C, F = 1.0MHz)
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
PIN DESCRIPTION
Pin Names
Description
OE
3–StateOutputEnableInput(ActiveLOW)
Dx
DataInputs(1)
Qx
3-StateOutputs
CLK
Clock Input
CLKEN
Clock Enable Input (Active LOW)
N C
NoInternalConnection
FUNCTION TABLE (EACHFLIP-FLOP)(1)
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑ = LOW-to-HIGH transition
2. Output level before the indicated steady-state input conditions were established.
Inputs
Output
OE
CLKEN
CLK
Dx
Qx
LH
X
X
Q
0
(2)
LL
HH
LL
LL
L
L
L or H
X
Q
0
(2)
HX
X
X
Z
GND
GND
GND
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
48
49
50
51
52
53
54
55
56
1
GND
GND
GND
25
26
27
28
32
31
30
29
CLK
D1
D2
OE
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
Q18
Q19
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
VCC
D17
D18
D19
GND
VCC
D20
CLKEN
VCC
VCC
GND
Q20
NC


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