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74F395 Datasheet(PDF) 1 Page - NXP Semiconductors

Part No. 74F395
Description  4-bit cascadable shift register 3-State
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74F395 Datasheet(HTML) 1 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74F395
4-bit cascadable shift register (3-State)
1
1990 Oct 23
853–0370 00780
FEATURES
4-bit parallel load shift register
Independent 3-State buffer outputs, Q0–Q3
Separate Qs output for serial expansion
Asynchronous Master Reset
DESCRIPTION
The 74F395 is a 4-bit Shift Register with serial and parallel
synchronous operating modes and 3-State buffer outputs. The
shifting and loading operations are controlled by the state of the
Parallel Enable (PE) input. When PE is High, data is loaded from the
Parallel Data inputs (D0–D3) into the register synchronous with the
High-to-Low transition of the Clock input (CP). When PE is Low, the
data at the Serial Data input (Ds) is loaded into the Q0 flip-flop, and
the data in the register is shifted one bit to the right in the direction
(Q0
!Q1!Q2!Q3) synchronous with the negative clock transition.
The PE and Data inputs are fully edge-triggered and must be stable
one setup prior to the High-to-Low transition of the clock.
The Master Reset (MR) is an asynchronous active-Low input. When
Low, the MR overrides the clock and all other inputs and clears the
register.
The 3-state output buffers are designed to drive heavily loaded
3-State buses, or large capacitive loads.
The active-Low Output Enable (OE) controls all four 3-State buffers
independent of the register operation. The data in the register
appears at the outputs when OE is Low. The outputs are in High
impedance “OFF” state, which means they will neither drive nor load
the bus when OE is High. The output from the last stage is brought
out separately. This output (Qs) is tied to the Serial Data input (Ds)
of the next register for serial expansion applications. The Qs output
is not affected by the 3-State buffer operation.
PIN CONFIGURATION
16
15
14
13
12
11
10
7
6
5
4
3
2
1
PE
VCC
Q3
Qs
CP
Q2
Q0
Q1
MR
Ds
D3
D0
D1
D2
SF00940
9
8
GND
OE
TYPE
TYPICAL fMAX
TYPICAL SUPPLY CURRENT
(TOTAL)
74F395
120MHz
32mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
16-pin plastic DIP
N74F395N
16-pin plastic SO
N74F395D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0 – D3
Data inputs
1.0/1.0
20
µA/0.6mA
Ds
Serial data input
1.0/1.0
20
µA/0.6mA
PE
Parallel Enable input
1.0/1.0
20
µA/0.6mA
MR
Master Reset input (active Low)
1.0/1.0
20
µA/0.6mA
OE
Output Enable input (active Low)
1.0/1.0
20
µA/0.6mA
CP
Clock Pulse input (active falling edge)
1.0/1.0
20
µA/0.6mA
Qs
Serial expansion output
50/33
1.0mA/20mA
Q0–Q3
Data outputs (3-State)
150/40
3.0mA/24mA
NOTE:
One (1.0) FAST unit load is defined as: 20
µA in the High state and 0.6mA in the Low state.


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