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74F353 Datasheet(PDF) 2 Page - NXP Semiconductors |
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74F353 Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 10 page Philips Semiconductors Product specification 74F353 Dual 4-input multiplexer (3-State) 2 1996 Jan 05 853–0103 16188 FEATURES • Inverting version of 74F253 • 3-State outputs for bus interface and multiplex expansion • Common select inputs • Separate Output Enable Inputs DESCRIPTION The 74F353 has two identical 4-input multiplexers with 3-State outputs which select two bits from four sources selected by common Select inputs (S0, S1). When the individual Output Enable (OEa, OEb) inputs of the 4-input multiplexers are High, the outputs are forced to a high impedance (Hi-Z) state. The 74F353 is the logic implementation of a 2-pole, 4-position switch; the position of the switch being determined by the logic levels supplied to the two common Select inputs. To avoid exceeding the maximum current ratings when the outputs of the 3-State devices are tied together, all but one device must be in the high-impedance state. Therefore, only one Output Enable must be active at a time. PIN CONFIGURATION 16 15 14 13 12 11 10 7 6 5 4 3 2 1 Ya VCC I2b I1b I0b I3b OEb S0 OEa S1 I0a I3a I2a I1a 9 8 GND Yb SF00891 TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74F353 6.0ns 11mA ORDERING INFORMATION DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C PACKAGE DRAWING NUMBER 16-pin plastic DIP N74F353N SOT38-4 16-pin plastic SO N74F353D SOT162-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW I0a–I3a Port A data inputs 1.0/1.0 20 µA/0.6mA I0b–I3b Port B data inputs 1.0/1.0 20 µA/0.6mA S0, S1 Common Select inputs 1.0/1.0 20 µA/0.6mA OEa Port A Output Enable input (active Low) 1.0/1.0 20 µA/0.6mA OEb Port B Output Enable input (active Low) 1.0/1.0 20 µA/0.6mA Ya, Yb 3-State outputs 150/40 3mA/24mA NOTE: One (1.0) FAST unit load is defined as: 20 µA in the High state and 0.6mA in the Low state. LOGIC SYMBOL 3 4 5 VCC = Pin 16 GND = Pin 8 SF00892 9 7 14 2 1 S0 S1 OEa 15 6 13 12 11 10 OEb Ya Yb I0a I1a I2a I3a I0b I1b I2b I3b IEC/IEEE SYMBOL SF00893 MUX 1 6 15 10 11 7 9 0 5 2 EN 4 3 13 12 1 3 0 G 0 3 1 14 2 |
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