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N74F299D Datasheet(PDF) 2 Page - NXP Semiconductors |
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N74F299D Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 14 page Philips Semiconductors Product specification 74F299 8-bit universal shift/storage register (3-State) 2 1990 Mar 01 853-0365 98989 FEATURES • Common parallel I/O for reduced pin count • Additional serial inputs and outputs for expansion • Four operating modes: Shift left, shift right, load and store • 3-State outputs for bus-oriented applications DESCRIPTION The 74F299 is an 8-bit universal shift/storage register with 3-State outputs. Four modes of operation are possible: Hold (store), shift left, shift right and parallel load. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs are provided for flip-flops Q0 and Q7 to allow easy serial cascading. A separate active-Low Master Reset is used to reset the register. The 74F299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as shown in the Function Table. All flip-flop outputs are brought out through 3-State buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A Low signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of clock are observed. A High signal on either OE0 or OE1 disables the 3-State buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-State buffers are also disabled by High signals on both S0 and S1 in preparation for a parallel load operation. PIN CONFIGURATION 20 19 18 17 16 15 14 13 12 10 11 9 8 7 6 5 4 3 2 1 VCC S1 DS7 Q7 I/O7 I/O5 I/O3 I/O1 DS0 S0 I/O6 I/O4 I/O2 I/O0 Q0 OE0 OE1 MR GND CP SF00865 TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74F299 115MHz 58mA ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C PKG DWG # 20-pin plastic DIP N74F299N SOT146-1 20-pin plastic SOL N74F299D SOT163-1 20-pin plastic SSOP II N74F299DB SOT339-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW DS0 Serial data input for right shift 1.0/1.0 20 µA/0.6mA DS7 Serial data input for left shift 1.0/1.0 20 µA/0.6mA S0, S1 Mode select inputs 1.0/2.0 20 µA/1.2mA CP Clock pulse input (Active rising edge) 1.0/1.0 20 µA/0.6mA MR Asynchronous Master Reset input (Active Low) 1.0/1.0 20 µA/0.6mA OE0, OE1 Output Enable input (Active Low) 1.0/1.0 20 µA/0.6mA Q0, Q7 Serial outputs 50/33 1.0mA/20mA I/On Multiplexed parallel data inputs or 3.5/1.0 70 µA/0.6mA I/On 3-State parallel outputs 150/40 3.0mA/24mA NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20 µA in the High State and 0.6mA in the Low state. |
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