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A6250X16W Datasheet(PDF) 11 Page - EM Microelectronic - MARIN SA |
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A6250X16W Datasheet(HTML) 11 Page - EM Microelectronic - MARIN SA |
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11 / 13 page  11 A6250 Timer Clearing and RES Action The watchdog circuit monitors the activity of the proces- sor. If the user’s software does not send a pulse to the TCL input within the programmed open window timeout period a short watchdog RES pulse is generated which is equal to T WD / 40 = 2.5 ms typically (see Fig. 5). With the open window constraint new security is added to conventional watchdogs by monitoring both software cycle time and execution. Should software clear the watchdog too quickly (incorrect cycle time) or too slowly (incorrect exe- cution) it will cause the system to be reset. If software is stuck in a loop which includes the routine to clear the watchdog then a conventional watchdog would not make a system reset even though software is malfunctioning; the A6250 would make a system reset because the watch- dog would be cleared too quickly. If no TCL signal is ap- plied before the closed and open windows expire, RES will start to generate square waves of period (TCW + TOW + TWDR). The watchdog will remain in this state until the next TCL falling edge appears during an open window, or until a fresh power-up sequence. The system enable output, EN, can be used to prevent critical control functions being activated in the event of the system going into this failure mode (see section “Enable - EN Output"). The RES output must be pulled up to VOUTPUT even if the output is not used by the system (see Fig. 8). Combined Voltage and Timer Action The combination of voltage and timer actions is illustrated by the sequence of events shown in Fig. 6. On power-up, when the voltage at V IN reaches VREF, the power-on-reset, POR, delay is initialized and holds RES active for the time of the POR delay. A TCL pulse will have no effect until this power-on-reset delay is completed. After the POR delay has elapsed, RES goes inactive and the watchdog timer starts acting. If no TCL pulse occurs, RES goes active low for a short time TWDR after each closed and open window period. A TCL pulse coming during the open window clears the watchdog timer. When the TCL pulse occurs too early (during the closed window), RES goes active and a new timeout sequence starts. A voltage drop below the VREF level for longer than typically 5 µs overrides the timer and immediately forces RES active and EN inactive. Any further TCL pulse has no effect until the next power-up sequence has completed. Enable - EN Output The system enable output, EN, is inactive always when RES is active and remains inactive after a RES pulse until the watchdog is serviced correctly 3 consecutive times (ie. the TCL pulse must come in the open window). After three consecutive services of the watchdog with TCL dur- ing the open window, the EN goes active low. A malfunc- tioning system would be repeatedly reset by the watchdog. In a conventional system critical motor con- trols could be energized each time reset goes inactive (time allowed for the system to restart) and in this way the electrical motors driven by the system could function out of control. The A6250 prevents the above failure mode by using the EN output to disable the motor controls until software has successfully cleared the watchdog three times (ie. the system has correctly restarted after a reset condition). Typical Application A6250 Fig. 18 |
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