Philips Semiconductors

Product specification

74F251A

8-input multiplexer (3-State)

1

1996 Jan 05

853–0358 16191

FEATURES

DESCRIPTION

The 74F251A is a logic implementation of a single 8-position switch

with the switch position controlled by the state of three Select (S0,

S1, S2) inputs. True (Y) and complementary (Y) outputs are both

provided. The output enable (OE) is active Low. When OE is High,

both outputs are in High impedance state, allowing multiple output

connections to a common bus without driving nor loading the bus

significantly. All but one device must be in High impedance state to

avoid high currents that would exceed the maximum ratings when

the outputs of the 3-State devices are tied together. When the output

of more than one device is tied together the user must ensure that

there is no overlap in the active Low portion of the output enable

voltages.

PIN CONFIGURATION

16

15

14

13

12

11

10

7

6

5

4

3

2

1

OE

I7

S0

S1

I6

I4

I5

I3

I2

Y

I1

I0

Y

9

8

GND

S2

SF00778

TYPE

TYPICAL

PROPAGATION

DELAY

TYPICAL

SUPPLY CURRENT

(TOTAL)

74F251A

4.5ns

19mA

ORDERING INFORMATION

DESCRIPTION

ORDER CODE

PKG

DESCRIPTION

COMMERCIAL RANGE

PKG

DWG #

16-pin plastic DIP

N74F251AN

SOT38-4

16-pin plastic SO

N74F251AD

SOT162-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F (U.L.) HIGH/LOW

LOAD VALUE HIGH/LOW

I0–I7

Data inputs

1.0/1.0

20

µA/0.6mA

S0–S2

Select inputs

1.0/1.0

20

µA/0.6mA

OE

Output Enable input (active Low)

1.0/1.0

20

µA/0.6mA

Y, Y

Data outputs

150/40

3mA/24mA

NOTE:

One (1.0) FAST unit load is defined as: 20

µA in the High state and 0.6mA in the Low state.

LOGIC SYMBOL

1

2

3

GND = Pin 8

SF00779

6

5

11

10

9

S0

S1

S2

7

4

12

13

14

15

OE

YY

I0

I1

I2

I3

I4

I5

I6

I7

IEC/IEEE SYMBOL

SF00780

MUX

7

11

3

2

1

5

6

0

G

0

7

10

2

EN

9

4

14

13

12

15