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MC14LC5480DW Datasheet(PDF) 8 Page - Freescale Semiconductor, Inc |
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MC14LC5480DW Datasheet(HTML) 8 Page - Freescale Semiconductor, Inc |
8 / 24 page FSR pin controls whether the B1 channel or the B2 channel is used for both transmit and receive PCM data word trans- fers. When the FSR pin is low, the transmit and receive PCM words are transferred in the B1 channel, and for FSR high the B2 channel is selected. The start of the B2 channel is ten IDL CLK cycles after the start of the B1 channel. The IDL SYNC (FST, Pin 14) is the input for the IDL frame synchronization signal. The signal at this pin is nominally high for one cycle of the IDL Clock signal and is rising edge aligned with the IDL Clock signal. (Refer to Figure 4 and the IDL Timing specifications for more details.) This event identi- fies the beginning of the IDL frame. The frequency of the IDL Sync signal is 8 kHz. The rising edge of the IDL SYNC (FST) should be aligned approximately with the rising edge of MCLK. MCLK must be one of the clock frequencies specified in the Digital Switching Characteristics table, and is typically tied to IDL CLK (BCLKT). The IDL CLK (BCLKT, Pin 12) is the input for the PCM data clock. All IDL PCM transfers and data control sequenc- ing are controlled by this clock following the IDL SYNC. This pin accepts an IDL data clock frequency of 256 kHz to 4.096 MHz. The IDL TX (DT, Pin 13) is the output for the transmit PCM data word. Data bits are output for the B1 channel on se- quential rising edges of the IDL CLK signal beginning after the IDL SYNC pulse. If the B2 channel is selected, then the PCM word transfer starts on the eleventh IDL CLK rising edge after the IDL SYNC pulse. The IDL TX pin will remain low impedance for the duration of the PCM word until the LSB after the falling edge of IDL CLK. The IDL TX pin will re- main in a high impedance state when not outputting PCM data or when a valid IDL Sync signal is missing. The IDL RX (DR, Pin 8) is the input for the receive PCM data word. Data bits are input for the B1 channel on sequen- tial falling edges of the IDL CLK signal beginning after the IDL SYNC pulse. If the B2 channel is selected, then the PCM word is latched in starting on the eleventh IDL CLK falling edge after the IDL SYNC pulse. General Circuit Interface (GCI) The General Circuit Interface (GCI) is the second of two standard synchronous 2B+D ISDN timing interface modes with which this device is compatible. In the GCI mode, the device can communicate in either of the two 64 kbps B– channels. (Refer to Figure 2d for sample timing.) The GCI mode is selected when the BCLKR pin is held low for two or more FST (FSC) rising edges. The digital pins that control the transmit and receive PCM word transfers are repro- grammed to accommodate this mode. The pins affected are FST, FSR, BCLKT, DT, and DR. The GCI Interface consists of four pins: FSC (FST), DCL (BCLKT), Dout (DT), and Din (DR). The GCI interface mode provides access to both the transmit and receive PCM data words with common control clocks of FSC (frame synchronization clock) and DCL (data clock). In this mode, the FSR pin controls whether the B1 channel or the B2 channel is used for both transmit and re- ceive PCM data word transfers. When the FSR pin is low, the transmit and receive PCM words are transferred in the B1 channel, and for FSR high the B2 channel is selected. The start of the B2 channel is 16 DCL cycles after the start of the B1 channel. The FSC (FST, Pin 14) is the input for the GCI frame syn- chronization signal. The signal at this pin is nominally rising edge aligned with the DCL clock signal. (Refer to Figure 6 and the GCI Timing specifications for more details.) This event identifies the beginning of the GCI frame. The frequen- cy of the FSC synchronization signal is 8 kHz. The rising edge of the FSC (FST) should be aligned approximately with the rising edge of MCLK. MCLK must be one of the clock fre- quencies specified in the Digital Switching Characteristics table, and is typically tied to DCL (BCLKT). The DCL (BCLKT, Pin 12) is the input for the clock that controls the PCM data transfers. The clock applied at the DCL input is twice the actual PCM data rate. The GCI frame begins with the logical AND of the FSC with the DCL. This event initiates the PCM data word transfers for both transmit and receive. This pin accepts a GCI data clock frequency of 512 kHz to 6.176 MHz for PCM data rates of 256 kHz to 3.088 MHz. The GCI Dout (DT, Pin 13) is the output for the transmit PCM data word. Data bits are output for the B1 channel on alternate rising edges of the DCL clock signal, beginning with the FSC pulse. If the B2 channel is selected, then the PCM word transfer starts on the seventeenth DCL rising edge after the FSC rising edge. The Dout pin will remain low impedance for 15–1/2 DCL clock cycles. The Dout pin becomes high impedance after the second falling edge of the DCL clock during the LSB of the PCM word. The Dout pin will remain in a high–impedance state when not outputting PCM data or when a valid FSC signal is missing. The Din (DR, Pin 8) is the input for the receive PCM data word. Data bits are latched in for the B1 channel on alternate rising edges of the DCL clock signal, beginning with the se- cond DCL clock after the rising edge of the FSC pulse. If the B2 channel is selected then the PCM word is latched in start- ing on the eighteenth DCL rising edge after the FSC rising edge. PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS The MC14LC5480 is manufactured using high–speed CMOS VLSI technology to implement the complex analog signal processing functions of a PCM Codec–Filter. The ful- ly–differential analog circuit design techniques used for this device result in superior performance for the switched capac- itor filters, the analog–to–digital converter (ADC) and the dig- ital–to–analog converter (DAC). Special attention was given to the design of this device to reduce the sensitivities of noise, including power supply rejection and susceptibility to radio frequency noise. This special attention to design in- cludes a fifth order low–pass filter, followed by a third order high–pass filter whose output is converted to a digital signal with greater than 75 dB of dynamic range, all operating on a single 5 V power supply. This results in a Mu–Law LSB size for small audio signals of about 386 µV. The typical idle chan- nel noise level of this device is less than one LSB. In addition to the dynamic range of the codec–filter function of this de- vice, the input gain–setting op amp has the capability of greater than 35 dB of gain intended for an electret micro- phone interface. This device was designed for ease of implementation, but due to the large dynamic range and the noisy nature of the environment for this device (digital switches, radio tele- phones, DSP front–end, etc.) special care must be taken to assure optimum analog transmission performance. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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