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MSP430X43X Datasheet(PDF) 30 Page - Texas Instruments

Part No. MSP430X43X
Description  Mixed signal microcontroller
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

MSP430X43X Datasheet(HTML) 30 Page - Texas Instruments

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MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
30
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
output frequency
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f
(1
≤ ≤ 60 ≤ ≤ 7)
CL = 20 pF,
VCC = 2.2 V
DC
5
MH
f(Px.y)
(1
≤ x ≤ 6, 0 ≤ y ≤ 7)
CL = 20 F,
IL = ±1.5 mA
VCC = 3 V
DC
7.5
MHz
f(ACLK)
P1 1/TA0/MCLK P1 5/TACLK/
f(MCLK)
P1.1/TA0/MCLK, P1.5/TACLK/
ACLK P1 4/TBCLK/SMCLK
CL = 20 pF
f(System)
MHz
f(SMCLK)
ACLK P1.4/TBCLK/SMCLK
CL 20 F
f(System)
MHz
P1.5/TACLK/ACLK,
f(ACLK) = f(LFXT1) = f(XT1)
40%
60%
P1.5/TACLK/ACLK,
CL = 20 pF
f(ACLK) = f(LFXT1) = f(LF)
30%
70%
CL 20 F
VCC = 2.2 V / 3 V
f(ACLK) = f(LFXT1)
50%
P1.1/TA0/MCLK,
f(MCLK) = f(XT1)
40%
60%
t(Xdc)
Duty cycle of output frequency
P1.1/TA0/MCLK,
CL = 20 pF,
VCC = 2.2 V / 3 V
f(MCLK) = f(DCOCLK)
50%–
15 ns
50%
50%+
15 ns
P1.4/TBCLK/SMCLK,
f(SMCLK) = f(XT2)
40%
60%
P1.4/TBCLK/SMCLK,
CL = 20 pF,
VCC = 2.2 V / 3 V
f(SMCLK) = f(DCOCLK)
50%–
15 ns
50%
50%+
15 ns
inputs Px.x, TAx, TBx
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
P t P1 P2 P1
t P2
t
l t i
i
l
2.2 V/3 V
1.5
cycle
t(int)
External interrupt timing
Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag, (see Note 1)
2.2 V
62
ns
(int)
g
for the interrupt flag, (see Note 1)
3 V
50
ns
TA0 TA1 TA2 (see Note 2)
2.2 V/3 V
1.5
cycle
t(cap)
Timer_A, Timer_B capture
TA0, TA1, TA2 (see Note 2)
2.2 V
62
t(cap)
_ ,
_
timing
TB0, TB1, TB2, TB3, TB4, TB5, TB6
(see Note 3)
3 V
50
ns
f(TAext)
Timer_A, Timer_B clock
frequency externally applied
TACLK TBCLK INCLK: t(H) t(L)
2.2 V
8
MHz
f(TBext)
frequency externally applied
to pin
TACLK, TBCLK, INCLK: t(H) = t(L)
3 V
10
MHz
f(TAint)
Timer_A, Timer_B clock
SMCLK or ACLK signal selected
2.2 V
8
MHz
f(BTAint)
Timer_A, Timer_B clock
frequency
SMCLK or ACLK signal selected
3 V
10
MHz
NOTES:
1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with
trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in
MCLK cycles.
2. The external capture signal triggers the capture event every time the minimum t(cap) cycle and time parameters are met. A capture
may be triggered with capture signals even shorter than t(cap). Both the cycle and timing specifications must be met to ensure a
correct capture of the 16-bit timer value and to ensure the flag is set.
3. Seven capture/compare registers in ’x44x and three capture/compare registers in ’x43x.
wake-up LPM3
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f = 1 MHz
6
td(LPM3)
Delay time
f = 2 MHz
VCC = 2.2 V/3 V
6
µs
td(LPM3)
Delay time
f = 3 MHz
VCC 2.2 V/3 V
6
µs


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