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74F199 Datasheet(PDF) 1 Page - NXP Semiconductors

Part No. 74F199
Description  8-bit parallel-access shift register
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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74F199 Datasheet(HTML) 1 Page - NXP Semiconductors

   
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Philips Semiconductors FAST Products
Product specification
74F199
8-bit parallel-access shift register
1
June 15, 1988
853–0082 93568
FEATURES
Buffered clock and control inputs
Shift right and parallel load capability
Fully synchronous data transfers
J-K(D) inputs to first stage
Clock enable for hold (do nothing) mode
Asynchronous Master Reset
DESCRIPTION
The 74F199 is an 8-bit Parallel Access Shift Register and its
functional characteristics are indicated in the Logic Diagram and
Function Table. The device is useful in a variety of shifting, counting
and storage applications. It performs serial, parallel, serial-to-parallel,
or parallel–to-serial data transfers at very high speeds.
The 74F199 operates in two primary modes: shift right (Q0
→Q1)
and parallel load, which are controlled by the state of the Parallel
Enable (PE) input. Serial data enters the first flip-flop (Q0) via the J
and K inputs when the PE input is High, and is shifted one bit in the
direction Q0
→Q1→Q2 following each Low-to-High clock transition.
The J and K inputs provide the flexibility of the J-K type input for
special applications, and by tying the two together the simple D-type
input is made for general applications.
The device appears as eight common clocked D flip-flops when the
PE input is Low. After the Low-to-High clock transition, data on the
parallel inputs (D0–D7) is transferred to the respective Q0–Q7
outputs.
All parallel and serial data transfers are synchronous, occurring after
each Low-to-High clock transition. The 74F199 utilizes
edge-triggered, therefore there is no restriction on the activity of the
J, K, Dn, and PE inputs for logic operation, other than the setup and
hold time requirements.
A Low on the Master Reset (MR) input overrides all other inputs and
clears the register asynchronously forcing all bit positions to a Low
state.
PIN CONFIGURATION
SF00152
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
K
J
D0
Q0
D1
Q1
D2
Q2
D3
Q3
CE
VCC
PE
D7
Q7
D6
Q6
D5
D4
Q5
Q4
MR
CP
GND
TYPE
TYPICAL fMAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
74F199
95MHz
70mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
24-pin plastic slim DIP
(300mil)
N74F199N
24-pin plastic SOL
N74F199D
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
D0–D7
Parallel data inputs
1.0/1.0
20
µA/0.6mA
J, K
J and K inputs
1.0/1.0
20
µA/0.6mA
PE
Parallel Enable input
1.0/1.0
20
µA/0.6mA
CE
Clock Enable input
1.0/1.0
20
µA/0.6mA
DP
Clock Pulse inputs (Active rising edge)
1.0/1.0
20
µA/0.6mA
MR
Master Reset input (Active Low)
1.0/1.0
20
µA/0.6mA
Q0–Q7
Data outputs
50/33
1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20
µA in the High state and 0.6mA in the Low state.


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