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IS80C32-12W Datasheet(PDF) 8 Page - Integrated Silicon Solution, Inc

Part # IS80C32-12W
Description  CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS80C32-12W Datasheet(HTML) 8 Page - Integrated Silicon Solution, Inc

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IS80C52
IS80C32
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
MC004-1D
11/19/98
ISSI®
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFR's) are located in
upper 128 Bytes direct addressing area. The SFR Memory
Map in Figure 6 shows that.
Not all of the addresses are occupied. Unoccupied
addresses are not implemented on the chip. Read
accesses to these addresses in general return random
data, and write accesses have no effect.
User software should not write 1s to these unimplemented
locations, since they may be used in future microcontrollers
to invoke new features. In that case, the reset or inactive
values of the new bits will always be 0, and their active
values will be 1.
The functions of the SFRs are outlined in the following
sections, and detailed in Table 2.
Accumulator (ACC)
ACC is the Accumulator register. The mnemonics for
Accumulator-specific instructions, however, refer to the
Accumulator simply as A.
B Register (B)
The B register is used during multiply and divide operations.
For other instructions it can be treated as another scratch
pad register.
Program Status Word (PSW). The PSW register contains
program status information.
Figure 6. Internal Data Memory and SFR Memory Map
Accessible
by Direct
Addressing
Accessible
by Indirect
Addressing
Only
Accessible
by Direct
and Indirect
Addressing
FFH
80H
7FH
0
FFH
80H
Upper
128
Lower
128
Special
Function
Registers
Ports,
Status and
Control Bits,
Timer,
Registers,
Stack Pointer,
Accumulator
(Etc.)
B
ACC
PSW
T2CON
IP
P3
IE
P2
SCON
P1
TCON
P0
Bit
Addressable
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
FF
F7
EF
E7
DF
D7
CF
C7
BF
B7
AF
A7
9F
97
8F
87
SBUF
TMOD
SP
RCAP2L
TL0
DPL
RCAP2H
TL1
DPH
TL2
TH0
TH2
TH1
PCON
Figure 7. Lower 128 Bytes of Internal RAM
78
70
68
60
58
50
48
40
38
30
28
20
18
10
08
00
7F
77
6F
67
5F
57
4F
47
3F
37
2F
27
1F
17
0F
07
...7F
0 ...
BANK3
BANK2
BANK 1
BANK 0
8 BYTES
REGISTER
BANKS
BIT
ADDRESSABLE
SEGMENT
SCRATCH
PAD
AREA


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