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IS64LV6416L Datasheet(PDF) 1 Page - Integrated Silicon Solution, Inc

Part No. IS64LV6416L
Description  64K x 16 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY
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Maker  ISSI [Integrated Silicon Solution, Inc]
Homepage  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS64LV6416L Datasheet(HTML) 1 Page - Integrated Silicon Solution, Inc

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IS64LV6416L
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
1
Rev. C
05/02/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
ISSI®
FEATURES
• High-speed access time: 10, 12 ns
• CMOS low power operation:
250 mW (typical) operating
250 µW (typical) standby
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Temperature offerings:
Option A1: –40oC to +85oC
Option A2: –40oC to +105oC
Option A3: –40oC to +125oC
DESCRIPTION
The
ISSI IS64LV6416L is a high-speed, 1,048,576-bit
static RAM organized as 65,536 words by 16 bits. It is
fabricated using
ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields access times
as fast as 10 ns with low power consumption.
When
CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip
Enable and Output Enable inputs,
CE and OE. The active
LOW Write Enable (
WE) controls both writing and reading
of the memory. A data byte allows Upper Byte (
UB) and
Lower Byte (
LB) access.
The IS64LV6416L is packaged in the JEDEC standard
44-pin TSOP-II, and 48-pin mini BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
MAY 2003
A0-A15
CE
OE
WE
64K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
64K x 16 HIGH-SPEED CMOS STATIC
RAM WITH 3.3V SUPPLY


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