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IS62LV256AL-20TLI Datasheet(PDF) 7 Page - Integrated Silicon Solution, Inc |
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IS62LV256AL-20TLI Datasheet(HTML) 7 Page - Integrated Silicon Solution, Inc |
7 / 14 page ISSI® Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 7 Rev. A 03/17/06 IS65LV256AL IS62LV256AL AC WAVEFORMS WRITE CYCLE NO. 1 ( WE WE WE WE WE Controlled)(1,2) DATA-IN VALID DATA UNDEFINED tWC tSCE tAW tHA tPWE tHZWE HIGH-Z tLZWE tSA tSD tHD ADDRESS CE WE DOUT DIN WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) -20 ns -45 ns Symbol Parameter Min. Max. Min. Max. Unit tWC Write Cycle Time 20 — 45 — ns tSCE CE to Write End 15 — 35 — ns tAW Address Setup Time to Write End 14 — 25 — ns tHA Address Hold from Write End 0 — 0 — ns tSA Address Setup Time 0 — 0 — ns tPWE(4) WE Pulse Width 14 — 25 — ns tSD Data Setup to Write End 13 — 20 — ns tHD Data Hold from Write End 0 — 0 — ns tHZWE(2) WE LOW to High-Z Output — 8 — 20 ns tLZWE(2) WE HIGH to Low-Z Output 0 — 0 — ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH. |
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