PCKEP14

2.5 V/3.3 V 1:5 differential ECL/PECL/HSTL clock driver

Rev. 01 — 30 October 2002

Product data

1.

Description

The PCKEP14 is a low skew 1-to-5 differential driver, designed with clock distribution

in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input

inputs can be used when the PCKEP14 is operating under PECL conditions.

The PCKEP14 specifically guarantees low output-to-output skew. Optimal design,

layout, and processing minimize skew within a device, and from device to device.

To ensure that the tight skew specification is realized, both sides of any differential

output need to be terminated identically into 50

Ω resistors, even if only one output is

being used. If an output pair is unused, both outputs may be left open (unterminated)

without affecting skew.

The common enable (EN) is synchronous, outputs are enabled/disabled in the LOW

state. This avoids a runt clock pulse when the device is enabled/disabled, as can

happen with an asynchronous control. The internal flip-flop is clocked on the falling

edge of the input clock, therefore, all associated specification limits are referenced to

the negative edge of the clock input.

supply in PECL mode. This allows the PCKEP14 to be used for high performance

clock distribution in +3.3 V or +2.5 V systems.

2.

Features