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IS61LF12832A Datasheet(PDF) 16 Page - Integrated Silicon Solution, Inc

Part No. IS61LF12832A
Description  128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS61LF12832A Datasheet(HTML) 16 Page - Integrated Silicon Solution, Inc

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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
08/11/05
ISSI®
IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A
IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A
READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
6.5
7.5
Symbol
Parameter
Min.
Max.
Min. Max.
Unit
fmax
Clock Frequency
133
117
MHz
tKC
Cycle Time
7.5
8.5
ns
tKH
Clock High Time
2.2
2.5
ns
tKL
Clock Low Time
2.2
2.5
ns
tKQ
Clock Access Time
6.5
7.5
ns
tKQX(2)
Clock High to Output Invalid
2.5
2.5
ns
tKQLZ(2,3)
Clock High to Output Low-Z
2.5
2.5
ns
tKQHZ(2,3)
Clock High to Output High-Z
3.8
4.0
ns
tOEQ
Output Enable to Output Valid
3.2
3.4
ns
tOEQX(2)
Output Enable to Output Invalid
2.5
2.5
ns
tOELZ(2,3)
Output Enable to Output Low-Z
0
0
ns
tOEHZ(2,3)
Output Disable to Output High-Z
3.5
3.5
ns
tAS
Address Setup Time
1.5
1.5
ns
tWS
Read/Write Setup Time
1.5
1.5
ns
tCES
Chip Enable Setup Time
1.5
1.5
ns
tAVS
Address Advance Setup Time
1.5
1.5
ns
tDS
Data Setup Time
1.5
1.5
ns
tAH
Address Hold Time
0.5
0.5
ns
tWH
Write Hold Time
0.5
0.5
ns
tCEH
Chip Enable Hold Time
0.5
0.5
ns
tAVH
Address Advance Hold Time
0.5
0.5
ns
tDH
Data Hold Time
0.5
0.5
ns
tPDS
ZZ High to Power Down
2
2
cyc
tPUS
ZZ Low to Power Down
2
2
cyc
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.


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