8

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. B

07/09/04

36 Mb (1M x 36 & 2M x 18)

DDR-II (Burst of 4) CIO Synchronous SRAMs

Timing Reference Diagram for Truth Table

Mode

Clock

Controls

Data Out / Data In

KLD

tt+1

t+2

A

K Clock

K Clock

LD

Clock

Cycle

NOP

Read A

B

Write B

Clock

LD

R / W

Address

Data-In/Out (DQ)

C Clock

C

tt+1

t+2

A

K Clock

K

Address

Data-In/Out (DQ)

C Clock

C

B

Write B

tt+1

t+2

A

K Clock

K

0,1,2,3

Address

Data-In/Out (DQ)

C Clock

C

NOP

Read A

0,1,2,3

Address

Data-In/Out (DQ)

C Clock

C Clock

CQ Clock

CQ Clock

Cycle

Timing Reference Diagram for Truth Table

Mode

Clock

Controls

Data Out / Data In

KLD

R/W

Stop Clock

Stop

X

X

Previous State

Previous State

Previous State

Previous State

No Operation (NOP)

L

→H

H

H

High-Z

High-Z

High-Z

High-Z

Read B

L

→H

LH

Dout at C (t +

1.5)

Dout at C

(t + 2)

Dout at C

(t + 2.5)

Dout at C

(t + 3)

Write A

L

→HL

L

Notes:

1. The internal burst counter is always fixed as two-bit.

2. X = don’t care; H = logic “1”; L = logic “0”.

3. A read operation is started when control signal R/W is active high.

4. A write operation is started when control signal R/W is active low.

5. Before entering into the stop clock, all pending read and write commands must be completed.

6. For timing definitions, refer to the AC Characteristics on page

16. Signals must have AC specifications at timings indicated in

parenthesis with respect to switching clocks K, K, C, and C.