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IS42S16160B-7BI Datasheet(PDF) 6 Page - Integrated Silicon Solution, Inc

Part # IS42S16160B-7BI
Description  32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS42S16160B-7BI Datasheet(HTML) 6 Page - Integrated Silicon Solution, Inc

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ISSI®
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION
Rev. 00E
05/25/06
IS42S83200B,
IS42S16160B
PIN FUNCTIONS
Symbol
Type
Function (In Detail)
A0-A12
Input Pin
Address Inputs: A0-A12 are sampled during the ACTIVE command (row-address A0-
A12) and READ/WRITE command (column address A0-A9 (x8), or A0-A8 (x16); with
A10 defining auto precharge) to select one location out of the memory array in the
respective bank. A10 is sampled during a PRECHARGE command to determine if all
banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The
address inputs also provide the op-code during a LOAD MODE REGISTER command.
BA0, BA1
Input Pin
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
CAS
Input Pin
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
CKE
Input Pin
The CKE input determines whether the CLK input is enabled. The next rising edge of the
CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE is LOW,
the device will be in either power-down mode, clock suspend mode, or self refresh
mode. CKE is an asynchronous input.
CLK
Input Pin
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
CS
Input Pin
The
CSinput determines whether command input is enabled within the device.
Command input is enabled when
CS is LOW, and disabled with CS is HIGH. The device
remains in the previous state when
CS is HIGH.
DQML,
Input Pin
DQML and DQMH control the lower and upper bytes of the I/O buffers. In read
DQMH
mode,DQML and DQMH control the output buffer. WhenDQML orDQMH is LOW, the
corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the
HIGH impedance state whenDQML/DQMH is HIGH. This function corresponds to
OE
in conventional DRAMs. In write mode,DQML and DQMH control the input buffer. When
DQML or DQMH is LOW, the corresponding buffer byte is enabled, and data can be
written to the device. WhenDQML or DQMH is HIGH, input data is masked and cannot
be written to the device. For IS42S16160B only.
DQM
Input Pin
For IS42S83200B only.
DQ0-DQ7 or
Input/Output
Data on the Data Bus is latched on DQ pins during Write commands, and buffered for
DQ0-DQ15
output after Read commands.
RAS
Input Pin
RAS, in conjunction with CAS and WE, forms the device command. See the "Command
Truth Table" item for details on device commands.
WE
Input Pin
WE, in conjunction with RAS and CAS, forms the device command. See the "Command
Truth Table" item for details on device commands.
VDDQ
Power Supply Pin
VDDQ is the output buffer power supply.
VDD
Power Supply Pin
VDD is the device internal power supply.
VSSQ
Power Supply Pin
VSSQ is the output buffer ground.
VSS
Power Supply Pin
VSS is the device internal ground.


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