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IS42VS16100C1 Datasheet(PDF) 33 Page - Integrated Silicon Solution, Inc |
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IS42VS16100C1 Datasheet(HTML) 33 Page - Integrated Silicon Solution, Inc |
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33 / 80 page  IS42VS16100C1 ISSI® Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 33 Rev. 00A 04/15/05 Read Cycle (Full Page) Interruption Using the Burst Stop Command The IS42VS16100C1 can output data continuously from the burst start address (a) to location a+255 during a read cycle in which the burst length is set to full page. The IS42VS16100C1 repeats the operation starting at the 256th cycle with the data output returning to location (a) and continuing with a+1, a+2, a+3, etc. A burst stop command must be executed to terminate this cycle. A precharge command must be executed within the ACT to PRE command period (tRAS max.) following the burst stop command. After the period (tRBD) required for burst data output to stop following the execution of the burst stop command has elapsed, the outputs go to the HIGH impedance state. This period (tRBD) is two clock cycle when the CAS latency is two and three clock cycle when the CAS latency is three. CAS CAS CAS CAS CAS Latency 3 2 tRBD 32 BST READ A0 COMMAND DQ CLK tRBD READ (CA=A, BANK 0) BURST STOP HI-Z DOUT A0 DOUT A0 DOUT A1 DOUT A2 COMMAND DQ CLK tRBD READ A0 READ (CA=A, BANK 0) BURST STOP BST HI-Z DOUT A0 DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A3 CAS latency = 3, burstlength = 4 CAS latency = 2, burstlength = 4 |
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