Integrated Silicon Solution, Inc. — 1-800-379-4774

1

Rev. B

04/18/05

IS41LV16105B

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

FEATURES

• TTL compatible inputs and outputs; tristate I/O

• Refresh Interval:

— 1,024 cycles/16 ms

• Refresh Mode:

—

RAS-Only, CAS-before-RAS (CBR), and Hidden

• JEDEC standard pinout

• Single power supply: 3.3V ± 10%

• Byte Write and Byte Read operation via two

CAS

• Lead-free available

DESCRIPTION

The

mance CMOS Dynamic Random Access Memories. Fast Page

Mode allows 1,024 random accesses within a single row with

access cycle time as short as 20 ns per 16-bit word. The Byte

Write control, of upper and lower byte, makes the IS41LV16105B

ideal for use in 16-, 32-bit wide data bus systems.

These features make the IS41LV16105B ideally suited for high-

bandwidth graphics, digital signal processing, high-performance

computing systems, and peripheral applications.

The IS41LV16105B is packaged in a 42-pin 400-mil SOJ and

400-mil 44- (50-) pin TSOP (Type II).

1M x 16 (16-MBIT) DYNAMIC RAM

WITH FAST PAGE MODE

KEY TIMING PARAMETERS

Parameter

-50

-60

Unit

Max.

60

ns

Max.

15

ns

30

ns

25

ns

84

104

ns

PIN CONFIGURATIONS

44(50)-Pin TSOP (Type II)

42-Pin SOJ

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

VDD

I/O0

I/O1

I/O2

I/O3

VDD

I/O4

I/O5

I/O6

I/O7

NC

NC

WE

RAS

NC

NC

A0

A1

A2

A3

VDD

GND

I/O15

I/O14

I/O13

I/O12

GND

I/O11

I/O10

I/O9

I/O8

NC

LCAS

UCAS

OE

A9

A8

A7

A6

A5

A4

GND

PIN DESCRIPTIONS

A0-A9

Address Inputs

I/O0-15

Data Inputs/Outputs

WE

Write Enable

OE

Output Enable

RAS

Row Address Strobe

UCAS

Upper Column Address Strobe

LCAS

Lower Column Address Strobe

Power

GND

Ground

NC

No Connection

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

VDD

I/O0

I/O1

I/O2

I/O3

VDD

I/O4

I/O5

I/O6

I/O7

NC

NC

NC

WE

RAS

NC

NC

A0

A1

A2

A3

VDD

GND

I/O15

I/O14

I/O13

I/O12

GND

I/O11

I/O10

I/O9

I/O8

NC

NC

LCAS

UCAS

OE

A9

A8

A7

A6

A5

A4

GND

APRIL 2005