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IS42S32200C1-6BL Datasheet(PDF) 9 Page - Integrated Silicon Solution, Inc |
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IS42S32200C1-6BL Datasheet(HTML) 9 Page - Integrated Silicon Solution, Inc |
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9 / 59 page  IS42S32200C1 ISSI® Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 9 Rev. 00E 05/18/06 TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n (1-6) CURRENT STATE COMMAND (ACTION) CS RAS CAS WE Any COMMAND INHIBIT (NOP/Continue previous operation) HX X X NO OPERATION (NOP/Continue previous operation) LH H H Idle ACTIVE (Select and activate row) L L H H AUTO REFRESH(7) LL L H LOAD MODE REGISTER(7) LL LL PRECHARGE(11) LL H L Row Active READ (Select column and start READ burst)(10) LH LH WRITE (Select column and start WRITE burst)(10) LH L L PRECHARGE (Deactivate row in bank or banks)(8) LL H L Read READ (Select column and start new READ burst)(10) LH LH (Auto WRITE (Select column and start WRITE burst)(10) LH L L Precharge PRECHARGE (Truncate READ burst, start PRECHARGE)(8) LL H L Disabled) BURST TERMINATE(9) LH HL Write READ (Select column and start READ burst)(10) LH LH (Auto WRITE (Select column and start new WRITE burst)(10) LH L L Precharge PRECHARGE (Truncate WRITE burst, start PRECHARGE)(8) LL H L Disabled) BURST TERMINATE(9) LH HL TRUTH TABLE – CKE (1-4) CURRENT STATE COMMANDn ACTIONn CKEn-1 CKEn Power-Down X Maintain Power-Down L L Self Refresh X Maintain Self Refresh L L Clock Suspend X Maintain Clock Suspend L L Power-Down (5) COMMAND INHIBIT or NOP Exit Power-Down L H Self Refresh (6) COMMAND INHIBIT or NOP Exit Self Refresh L H Clock Suspend (7) X Exit Clock Suspend L H All Banks Idle COMMAND INHIBIT or NOP Power-Down Entry H L All Banks Idle AUTO REFRESH Self Refresh Entry H L Reading or Writing VALID Clock Suspend Entry H L See TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK n HH NOTES: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMANDn is the command registered at clock edge n, and ACTONn is a result of COMMANDn. 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n+1 (provided that tCKS is met). 6. Exiting self refresh at clock edge n will put the device in all banks idle state once tXSR is met. COMMAND INHIBIT or NOP commands should be issued on clock edges occurring during the tXSR period. A minimum of two NOP commands must be sent during tXSR period. 7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n+1. |
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