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IS42S81600B-6T Datasheet(PDF) 11 Page - Integrated Silicon Solution, Inc

Part # IS42S81600B-6T
Description  16Meg x 8, 8Meg x16 128-MBIT SYNCHRONOUS DRAM
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS42S81600B-6T Datasheet(HTML) 11 Page - Integrated Silicon Solution, Inc

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
11
Rev. E
05/01/06
ISSI®
IS42S81600B,
IS42S16800B
Current State
CS
CS
CS
CS
CS
RAS
RAS
RAS
RAS
RAS CAS
CAS
CAS
CAS
CAS
WE
WE
WE
WE
WE
Address
Command
Action
Write Recovering
H
×
×
×
×
DESL
Nop, Enter row active after tDPL
L
H
H
H
×
NOP
Nop, Enter row active after tDPL
L
H
H
L
×
BST
Nop, Enter row active after tDPL
L
H
L
H
BA, CA, A10
READ/READA
Begin read (8)
L
H
L
L
BA, CA, A10
WRIT/ WRITA
Begin new write
L
L
H
H
BA, RA
ACT
ILLEGAL (3)
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL (3)
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
OC, BA
MRS
ILLEGAL
Write Recovering
H
×
×
×
×
DESL
Nop, Enter precharge after tDPL
with Auto
L
H
H
H
×
NOP
Nop, Enter precharge after tDPL
Precharge
L
H
H
L
×
BST
Nop, Enter row active after tDPL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL(3,8,11)
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL (3,11)
L
L
H
H
BA, RA
ACT
ILLEGAL (3,11)
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL (3,11)
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
OC, BA
MRS
ILLEGAL
Refresh
H
×
×
×
×
DESL
Nop, Enter idle after tRC
L
H
H
×
×
NOP/BST
Nop, Enter idle after tRC
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
OC, BA
MRS
ILLEGAL
Mode Register
H
×
×
×
×
DESL
Nop, Enter idle after 2 clocks
Accessing
L
H
H
H
×
NOP
Nop, Enter idle after 2 clocks
L
H
H
L
×
BST
ILLEGAL
L
H
L
×
BA, CA, A10
READ/WRITE
ILLEGAL
L
L
×
×
BA, RA
ACT/PRE/PALL
ILLEGAL
REF/MRS
FUNCTIONAL TRUTH TABLE Continued:
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
Notes:
1. All entries assume that CKE is active (CKEn-1=CKEn=H).
2. If both banks are idle, and CKE is inactive (Low), the device will enter Power Down mode. All input buffers except CKE will
be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the
state of that bank.
4. If both banks are idle, and CKE is inactive (Low), the device will enter Self-Refresh mode. All input buffers except CKE will
be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don’t satisfy tDPL.
10. Illegal if tRRD is not satisfied.
11. Illegal for single bank, but legal for other banks.


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