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IC62LV1024AL-70QI Datasheet(PDF) 9 Page - Integrated Circuit Solution Inc |
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IC62LV1024AL-70QI Datasheet(HTML) 9 Page - Integrated Circuit Solution Inc |
9 / 11 page Integrated Circuit Solution Inc. 9 LPSR017-0A 09/13/2001 IC62LV1024AL IC62LV1024ALL WRITE CYCLE NO. 2 ( CE1 CE1 CE1 CE1 CE1, CE2 Controlled)(1,2) HIGH-Z DATA UNDEFINED DATA-IN VALID tWC tSCE1 tSA tHA tSCE2 tPWE(4) tAW tHZWE tSD tHD tLZWE ADDRESS DIN CE1 CE2 WE DOUT Notes: 1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE = VIH. DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter TestCondition Min. Max. Unit VDR Vcc for Data Retention See Data Retention Waveform 2.0 3.3 V IDR Data Retention Current Vcc = 2.0V, CE1 ≥ Vcc – 0.2V Com. (-L) — 30 µA Com. (-LL) — 5 µA Ind. (-L) — 50 µA Ind. (-LL) — 10 µA tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns tRDR Recovery Time See Data Retention Waveform tRC —ns DATA RETENTION WAVEFORM ( CE1 CE1 CE1 CE1 CE1 Controlled) VCC CE1 ≥ VCC - 0.2V tSDR tRDR VDR CE1 GND 3.0V 2.2V Data Retention Mode |
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